Cache memory system including a partially hashed index
AssigneeSun Microsystems, Inc.
InventorRobert E. Cypher
Life of this patent
Estimating the term…
Abstract
In one embodiment, a cache memory system includes a cache memory coupled to a cache controller. The cache memory controller may receive an address and generate an index value corresponding to the address for accessing a particular entry within the cache memory. More particularly, the cache controller may generate the index value by performing a hash function on a first portion of the address such as an address tag, and combining a result of the hash function with a second portion of the address such as an index, for example.
Claims11
A cache memory system comprising:
- a cache memory;
- and
- a cache controller coupled to the cache memory, wherein the cache memory controller is configured to receive an address and to generate an index value corresponding to the address for accessing a particular entry within the cache memory;
- wherein the cache controller is configured to generate the index value by performing a hash function on a first portion of the address and by combining a result of the hash function with a second portion of the address;
- wherein performing the hash function includes performing a first bit-wise Exclusive-Or (XOR) operation on groups of selected bits of the first portion of the address;
- and
- wherein the combining includes:
- performing a second bit-wise Exclusive-Or operation between a first subset of bits of the second portion of the address and the result of the hash function;
- and
- concatenating a second subset of the second portion with the result of the first bit-wise Exclusive-Or operation.
A method of accessing a cache memory, the method comprising:
- receiving an address;
- and
- generating an index value corresponding to the address for accessing a particular entry within the cache memory;
- wherein generating an index value includes:
- performing a hash function on a first portion of the address by performing a first bit-wise Exclusive-Or operation on groups of selected bits of the first portion of the address;
- and
- combining a result of the hash function with a second portion of the address including:
- performing a second bit-wise Exclusive-Or operation between a first subset of bits of the second portion of the address and the result of the hash function;
- and
- concatenating a second subset of the second portion with the result of the first bit-wise Exclusive-Or operation.
A computer system comprising:
- a system memory;
- a processor coupled to the system memory via a bus;
- wherein the processor includes a cache memory system including:
- a cache memory;
- and
- a cache controller coupled to the cache memory, wherein the cache memory controller is configured to receive an address and to generate an index value corresponding to the address for accessing a particular entry within the cache memory;
- wherein the cache controller is configured to generate the index value by performing a hash function on a first portion of the address and by combining a result of the hash function with a second portion of the address;
- wherein performing the hash function includes performing a bit-wise Exclusive-Or (XOR) operation on groups of selected bits of the first portion of the address;
- and
- wherein the combining includes:
- performing a second bit-wise Exclusive-Or operation between a first subset of bits of the second portion of the address and the result of the hash function;
- and
- concatenating a second subset of the second portion with the result of the first bit-wise Exclusive-Or operation.
Dependencies are inferred from the claim text.