Augmented instruction set for proactive synchronization within a computer system
AssigneeAdvanced Micro Devices, Inc.
InventorMitchell Alsup
Life of this patent
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Abstract
Providing proactive synchronization in a computer system may include providing an augmented instruction set with additional synchronizing instructions. Therefore, a method includes a processor executing a set of instructions to request exclusive access to a plurality of memory resources. The set of instructions includes an ACQUIRE instruction. In addition, the method may include storing addresses referenced by the set of instructions within a buffer. Further, the method may include sending the addresses referenced by the set of instructions, as a set, to be compared to other addresses to which exclusive access to memory addresses has been granted in response to execution of the ACQUIRE instruction.
Claims26
A method comprising:
- a processor that implements an x86 architecture executing a set of instructions comprising a critical code section to request exclusive access to a plurality of memory resources using a plurality of memory mov instructions each including an x86 lock instruction prefix, and each specifying a memory address of a respective one of the plurality of memory resources, wherein the set of instructions includes an acquire instruction that comes after the mov instructions in program order;
- storing each memory address referenced by the set of instructions within a processor buffer;
- wherein, in response to execution of the acquire instruction, sending each memory address stored within the processor buffer, as a set, to be compared to other addresses to which exclusive access has been granted.
A processor that implements an x86 architecture coupled to one or more memories and to one or more additional processors, the processor comprising:
- an execution pipeline configured to execute a set of instructions comprising a critical code section to request exclusive access to a given memory resources, wherein the critical code section includes a plurality of memory reference mov instructions, each including an x86 lock instruction prefix, and each specifying a memory address of the memory, wherein the set of instructions further includes an acquire instruction that comes after the mov instructions in program order;
- an interface unit including a buffer, wherein the interface unit is coupled to the instruction pipeline and configured to store each memory address referenced by the set of instructions within the buffer;
- wherein, in response to execution of the acquire instruction, the interface unit is further configured to send each memory address, as a set, to be compared to other addresses to which exclusive access has been granted.
A computer readable storage medium including a set of program instructions comprising a critical code section that is executable by a processor that implements an x86 architecture to:
- request exclusive access to a plurality of memory resources using a plurality of memory mov instructions each including an x86 lock instruction prefix, and each specifying a memory address of a respective one of the plurality of memory resources, wherein the set of program instructions includes an acquire instruction that comes after the mov instructions in program order;
- store each memory address referenced by the set of program instructions within a buffer of the processor;
- send each memory address stored within the processor buffer, as a set, to be compared to other addresses to which exclusive access has been granted in response to execution of the acquire instruction;
- wherein, in response to execution of the acquire instruction, sending each memory address stored within the processor buffer, as a set, to be compared to other addresses to which exclusive access been granted.
Dependencies are inferred from the claim text.