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US 7,606,980 B2Granted
Demand-based error correction
AssigneeIntel Corporation
InventorsMoinuddin K. Qureshi, Paul B. Racunas, Shubhendu S. Mukherjee
Life of this patent
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Abstract
A technique for demand-based error correction. More particularly, at least one embodiment of the invention relates to a technique to reduce storage overhead of cache memories containing error correction codes (ECC) while maintaining substantially the same performance of the cache.
Claims22
An apparatus comprising:
- a plurality of cache lines comprising circuitry;
- a plurality of error correcting code (ECC) storage areas coupled to the plurality of cache lines, the plurality of ECC storage areas being less than the number of cache lines, wherein the cache lines not in a modified state are to correspond to one of a number of error detection code (EDC) storage areas and not an ECC storage area.
A system comprising:
- a memory;
- a processor, comprising circuitry, coupled to the memory to write data to a plurality of cache lines, the cache lines to store less than or equal to a maximum number of modified data, the maximum modified data being less than the plurality of cache lines, wherein the plurality of cache lines include an identification (ID) field to indicate a corresponding ECC field to which a respective cache line corresponds.
A method comprising:
- issuing a write operation to a cache line array;
- writing back a modified data to memory if the cache line array contains a maximum number of modified cache lines, the maximum number of modified cache lines being less than all of the cache lines in the cache line array;
- writing the data to a clean cache line corresponding to the modified data;
- and
- updating an identification (ID) field in the clean cache line to point to an error correction code (ECC) field.
2 more elements
Dependencies are inferred from the claim text.