Automatic caching generation in network applications

A computer-implemented method, comprising:

• identifying a candidate representing a plurality of instructions of a plurality of threads that perform one or more external memory accesses, the one or more external memory accesses having an identical base address, including
• partitioning the plurality of instructions of the external memory accesses into one or more sets of potential candidates based on dependency relationships of the instructions,
• converting addresses of each external memory accesses into a form having a base address and an offset,
• screening out one or more ineligible candidates from the potential candidates, wherein the ineligible candidates include a base address that is different from a remainder of the potential candidates, and
• selecting one of the potential candidate sets as the candidate, instructions of the candidate satisfying a predetermined dependency relationship,
• inserting at least one of directives and instructions into an instruction stream corresponding to the identified candidate to maintain contents of at least one of a content addressable memory (CAM) and local memory (LM) of a processor and to modify at least one of the external memory accesses to access at least one of the CAM and LM of the processor without having to perform the respective external memory access.

A computer-implemented method, comprising:

• identifying a candidate representing a plurality of instructions of a plurality of threads that perform one or more external memory accesses, the one or more external memory accesses having an identical base address, including
• partitioning the plurality of instructions of the external memory accesses into one or more sets of potential candidates based on dependency relationships of the instructions,
• converting addresses of each external memory accesses into a form having a base address and an offset, and
• selecting one of the potential candidate sets as the candidate, instructions of the candidate satisfying a predetermined dependency relationship;
• and
• inserting at least one of directives and instructions into an instruction stream corresponding to the identified candidate to maintain contents of at least one of a content addressable memory (CAM) and local memory (LM) of a processor and to modify at least one of the external memory accesses to access at least one of the CAM and LM of the processor without having to perform the respective external memory access, including
• for each thread, reserving a sufficient space in the local memory to store data portions of cache lines, and
• inserting a caching instruction prior to each of the external memory accesses.

A machine-readable storage medium having executable code to cause a machine to perform a method, the method comprising:

• identifying a candidate representing a plurality of instructions of a plurality of threads that perform one or more external memory accesses, the one or more external memory accesses having an identical base address, including
• partitioning the plurality of instructions of the external memory accesses into one or more sets of potential candidates based on dependency relationships of the instructions,
• converting addresses of each external memory accesses into a form having a base address and an offset,
• grouping multiple potential candidates having the identical base address into a single candidate, wherein a group having most of the potential candidates is selected as a final candidate for caching, and
• selecting one of the potential candidate sets as the candidate, instructions of the candidate satisfying a predetermined dependency relationship;
• and
• inserting at least one of directives and instructions into an instruction stream corresponding to the identified candidate to maintain contents of at least one of a content addressable memory (CAM) and local memory (LM) of a processor and to modify at least one of the external memory accesses to access at least one of the CAM and LM of the processor without having to perform the respective external memory access.

A machine-readable storage medium having executable code to cause a machine to perform a method, the method comprising:

• identifying a candidate representing a plurality of instructions of a plurality of threads that perform one or more external memory accesses, the one or more external memory accesses having an identical base address, including
• partitioning the plurality of instructions of the external memory accesses into one or more sets of potential candidates based on dependency relationships of the instructions,
• converting addresses of each external memory accesses into a form having a base address and an offset,
• screening out one or more ineligible candidates from the potential candidates, wherein the ineligible candidates include a base address that is different from a remainder of the potential candidates, and
• selecting one of the potential candidate sets as the candidate, instructions of the candidate satisfying a predetermined dependency relationship,
• inserting at least one of directives and instructions into an instruction stream corresponding to the identified candidate to maintain contents of at least one of a content addressable memory (CAM) and local memory (LM) of a processor and to modify at least one of the external memory accesses to access at least one of the CAM and LM of the processor without having to perform the respective external memory access.

A machine-readable storage medium having executable code to cause a machine to perform a method, the method comprising:

• identifying a candidate representing a plurality of instructions of a plurality of threads that perform one or more external memory accesses, the one or more external memory accesses having an identical base address, including
• partitioning the plurality of instructions of the external memory accesses into one or more sets of potential candidates based on dependency relationships of the instructions,
• convening addresses of each external memory accesses into a form having a base address and an offset, and
• selecting one of the potential candidate sets as the candidate, instructions of the candidate satisfying a predetermined dependency relationship;
• and
• inserting at least one of directives and instructions into an instruction stream corresponding to the identified candidate to maintain contents of at least one of a content addressable memory (CAM) and local memory (LM) of a processor and to modify at least one of the external memory accesses to access at least one of the CAM and LM of the processor without having to perform the respective external memory access, including
• for each thread, reserving a sufficient space in the local memory to store data portions of cache lines, and
• inserting a caching instruction prior to each of the external memory accesses.

A data processing system, comprising:

• a processor;
• and
• a memory for storing instructions, which when executed from the memory, cause the processor to perform operations, including
• identifying a candidate representing a plurality of instructions of a plurality of threads that perform one or more external memory accesses, the one or more external memory accesses having an identical base address, including
• partitioning the plurality of instructions of the external memory accesses into one or more sets of potential candidates based on dependency relationships of the instructions,
• converting addresses of each external memory accesses into a form having a base address and an offset,
• grouping multiple potential candidates having the identical base address into a single candidate, wherein a group having most of the potential candidates is selected as a final candidate for caching, and
• selecting one of the potential candidate sets as the candidate, instructions of the candidate satisfying a predetermined dependency relationship;
• and
• inserting at least one of directives and instructions into an instruction stream corresponding to the identified candidate to maintain contents of at least one of a content addressable memory (CAM) and local memory (LM) of a processor and to modify at least one of the external memory accesses to access at least one of the CAM and LM of the processor without having to perform the respective external memory access.

A data processing system, comprising:

• a processor;
• and
• a memory for storing instructions, which when executed from the memory, cause the processor to perform operations, including
• identifying a candidate representing a plurality of instructions of a plurality of threads that perform one or more external memory accesses, the one or more external memory accesses having an identical base address, including
• partitioning the plurality of instructions of the external memory accesses into one or more sets of potential candidates based on dependency relationships of the instructions,
• converting addresses of each external memory accesses into a form having a base address and an offset,
• screening out one or more ineligible candidates from the potential candidates, wherein the ineligible candidates include a base address that is different from a remainder of the potential candidates, and
• selecting one of the potential candidate sets as the candidate, instructions of the candidate satisfying a predetermined dependency relationship,
• inserting at least one of directives and instructions into an instruction stream corresponding to the identified candidate to maintain contents of at least one of a content addressable memory (CAM) and local memory (LM) of a processor and to modify at least one of the external memory accesses to access at least one of the CAM and LM of the processor without having to perform the respective external memory access.

A data processing system, comprising:

• a processor;
• and
• a memory for storing instructions, which when executed from the memory, cause the processor to perform operations, including
• identifying a candidate representing a plurality of instructions of a plurality of threads that perform one or more external memory accesses, the one or more external memory accesses having an identical base address, including
• partitioning the plurality of instructions of the external memory accesses into one or more sets of potential candidates based on dependency relationships of the instructions,
• converting addresses of each external memory accesses into a form having a base address and an offset, and
• selecting one of the potential candidate sets as the candidate, instructions of the candidate satisfying a predetermined dependency relationship;
• and
• inserting at least one of directives and instructions into an instruction stream corresponding to the identified candidate to maintain contents of at least one of a content addressable memory (CAM) and local memory (LM) of a processor and to modify at least one of the external memory accesses to access at least one of the CAM and LM of the processor without having to perform the respective external memory access, including
• for each thread, reserving a sufficient space in the local memory to store data portions of cache lines, and
• inserting a caching instruction prior to each of the external memory accesses.