Programmable logic devices

A method comprising:

• configuring a plurality of embedded memory blocks in a programmable logic device, each of the plurality of embedded memory blocks coupled to a field programmable gate array memory core and a respective one of a plurality of address counters, by:
• shifting configuration data into a vertical shift register;
• configuring each of the embedded memory blocks with the respective address counter and data from the vertical shift register to select memory locations in the embedded memory block in which the shifted data is to be stored;
• and
• providing control signals for storing the data in the selected memory locations and starting the respective address counter;
• and
• reusing at least one of the plurality of address counters for general counter use after the embedded memory blocks are configured.

A programmable logic device, comprising:

• a plurality of memory blocks coupled to a field programmable gate array (FPGA) core;
• a vertical shift register (VSR) coupled to the plurality of memory blocks and the FPGA core to provide configuration data to the memory blocks;
• an HFF register coupled to the FPGA core;
• a control unit coupled to the VSR and HFF register for controlling the loading of data in the memory blocks;
• a plurality of address counters, each said address counter coupled to a respective said memory block to provide an address for selecting memory locations in the memory block, each said address counter adapted to be used as an up/down counter for general logic functions after configuration of the respective said memory block;
• and
• an address decoder connected between each said address counter and each said memory block and structured to enable access to selected memory locations in the memory block.

A system comprising in a programmable logic device having a field programmable gate array memory core and a plurality of embedded memory blocks coupled to the memory core, comprising:

• means for shifting configuration data into a vertical shift register;
• means for configuring each embedded memory block with an address counter and data from the vertical shift register to select memory locations in each embedded memory block in which the shifted data is to be stored, wherein the address counter is also adapted for use as an up/down counter to implement LIFO or FIFO functions;
• and
• means for providing control signals for storing the data in the selected memory locations and starting the address counter.

A method for configuring embedded block memories in a programmable logic device having a field programmable gate array memory core and a plurality of embedded memory blocks coupled to the memory core and a respective local counter coupled to each memory block, comprising:

• shifting configuration data into a vertical shift register;
• selecting memory locations in each said embedded memory block in which the shifted data is to be stored;
• and
• providing control signals for storing the data in the selected memory locations and starting the local counter;
• and
• reusing at least one said local counter after the embedded memory blocks are configured.

A programmable logic device comprising:

• a field programmable gate array memory core;
• a plurality of memory blocks coupled to the memory core;
• and
• a plurality of address counters, each of which being coupled to a respective one of the plurality of address counters to provide an address for selecting memory locations in the memory block to configure the plurality of memory blocks and at least one of the address counters being configured for use as a general use counter after the plurality of memory blocks are configured.