Frame transfer method and apparatus
AssigneeFujitsu Limited
InventorYuuji Konno
Life of this patent
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Abstract
In a frame transfer method and apparatus, a data entry into a content addressable memory is set to enable, and upon receipt of a transfer frame addressed to a first apparatus from a line bus, header information of the frame is entered into the content addressable memory based on the setting that the entry is enabled. The frame prepared based on header information entered into a content addressable memory of a second apparatus and transmitted by the second apparatus can be used, and the frame is discarded when it is not addressed to the first apparatus. Furthermore, normal frame processing is performed when the entry is not enabled by the setting.
Claims11
A frame transfer method comprising the steps of:
- setting to enable a data entry into a content addressable memory with an enable bit signal through a PCI bus;
- and
- entering, upon receipt of a transfer frame addressed to a first apparatus from a line bus which is faster in speed than the PCI bus, header information of the frame into the content addressable memory not through the PCI bus, based on the setting that the entry is enabled,
- the enable bit signal being set to OFF in a normal operation where the header information of the frame from the line bus is extracted for retrieval of the content addressable memory based on the header information and the frame is transferred only at a time of hit by the retrieval, and being set to ON in an entry operation of the content addressable memory where the header information of the frame from the line bus is extracted and is entered into the content addressable memory only when the header information is destined to the first apparatus itself.
A frame transfer apparatus comprising:
- means setting to enable a data entry into a content addressable memory with an enable bit signal through a PCI bus;
- and
- means entering, upon receipt of a transfer frame addressed to a first apparatus from a line bus which is faster in speed than the PCI bus, header information of the frame into the content addressable memory not through the PCI bus, based on the setting that the entry is enabled,
- the enable bit signal being set to OFF in a normal operation where the header information of the frame from the line bus is extracted for retrieval of the content addressable memory based on the header information and the frame is transferred only at a time of hit by the retrieval, and being set to ON in an entry operation of the content addressable memory where the header information of the frame from the line bus is extracted and is entered into the content addressable memory only when the header information is destined to the first apparatus itself.
Dependencies are inferred from the claim text.