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US 7,606,957 B2Granted
Bus system including a bus arbiter for arbitrating access requests
AssigneePanasonic Corporation
InventorTakanori Furuzono
Life of this patent
Estimating the term…
Abstract
A bus system is provided, which includes a shared resource, a shared bus, a plurality of requesters, and a bus arbiter for arbitrating access requests made by the plurality of requesters to access the shared resource through the shared bus. At least one of the plurality of requesters outputs, according to an internal state in that requester, an internal state signal indicating that the priority of an access request made by that requester needs to be changed. The bus arbiter arbitrates the access requests in accordance with the internal state signal.
Claims4
A bus system comprising:
- a shared resource;
- a shared bus;
- a plurality of requesters;
- and
- a bus arbiter for arbitrating access requests made by the plurality of requesters to access the shared resource through the shared bus,
- wherein at least one of the plurality of requesters has a cache memory and outputs, according to a cache hit rate of the cache memory, an internal state signal indicating that the priority of an access request made by that requester needs to be changed,
- the bus arbiter arbitrates the access requests in accordance with the internal state signal, and
- if a second cache hit rate, measured after an already measured first cache hit rate, is lower than a first value, which is lower than the first cache hit rate by a predetermined value, the requester having the cache memory makes the internal state signal indicate that the priority needs to be raised.
5 more elements
A bus system comprising:
- a shared resource;
- a shared bus;
- a plurality of requesters;
- and
- a bus arbiter for arbitrating access requests made by the plurality of requesters to access the shared resource through the shared bus,
- wherein at least one of the plurality of requesters outputs, according to an internal state in that requester, an internal state signal indicating that the priority of an access request made by that requester needs to be changed,
- the bus arbiter arbitrates the access requests in accordance with the internal state signal, and
- at least one of the at least one requester that outputs the internal state signal has an interrupt control section for controlling an interrupt occurring in that requester and generates the internal state signal of that requester in accordance with notification of occurrence of an interrupt from the interrupt control section.
5 more elements
Dependencies are inferred from the claim text.