Graphical programs with direct memory access FIFO for controller/FPGA communications

A memory medium that stores program instructions for communicating between programs executing respectively on a controller and a programmable hardware element, wherein the program instructions are computer- executable to perform:

• creating a first graphical program in response to first user input, wherein the first graphical program comprises a first plurality of interconnected nodes that visually indicate functionality of the first graphical program, wherein the first graphical program includes a first node that represents a direct memory access (DMA) structure;
• creating a second graphical program in response to second user input, wherein the second graphical program comprises a second plurality of interconnected nodes that visually indicate functionality of the second graphical program, wherein the second graphical program includes a second node that provides an interface to the DMA structure;
• automatically generating at least a portion of DMA logic in response to said including the first node and in accordance with configuration information for the DMA structure, wherein the at least a portion of DMA logic implements data transfer functionality for the DMA structure;
• deploying the first graphical program to the programmable hardware element, comprising:
• generating a hardware configuration program based on the first graphical program;
• and
• deploying the hardware configuration program on the programmable hardware element;
• deploying the at least a portion of DMA logic to the programmable hardware element to implement data transfer functionality for the DMA structure;
• deploying the second graphical program to the controller;
• wherein the first graphical program and the second graphical program are executable to communicate via the DMA structure to cooperatively perform a specified task.

A system for communicating between programs executing respectively on a controller and a programmable hardware element, the system comprising:

• the controller, comprising:
• a first processor;
• and
• a first memory, coupled to the processor;
• the programmable hardware element, coupled to the controller;
• and
• a computer system, coupled to the controller and the programmable hardware element, the computer system comprising:
• a second processor;
• and
• a second memory, coupled to the second processor;
• wherein the programmable hardware element is configured to implement a first graphical program comprising a first plurality of interconnected nodes that visually indicate functionality of the first graphical program, including a first node representing a direct memory access (DMA) structure, wherein a first portion of the DMA structure is implemented on the programmable hardware element, wherein a second portion of the DMA structure is implemented in the first memory;
• and
• wherein the first memory stores program instructions implementing a second graphical program comprising a second plurality of interconnected nodes that visually indicate functionality of the second graphical program, including a second node operable to provide a controller interface to the DMA structure, the system further comprising:
• a DMA controller comprised on or coupled to the programmable hardware element, wherein the DMA controller is operable to receive instructions from the first node and the second node and directly transfer data between the programmable hardware element and the first memory in accordance with the received instructions, wherein the DMA controller comprises:
• first DMA logic, coupled to or comprised on the programmable hardware element, wherein the first DMA logic implements DMA functionality;
• and
• second DMA logic, comprised on the programmable hardware element, wherein the second DMA logic implements structure functionality for the first DMA logic;
• wherein the program instructions stored in the second memory are further executable by the second processor to:
• automatically generate the second DMA logic in response to inclusion of the first node in the first graphical program and in accordance with configuration information for the DMA structure;
• deploy the first graphical program and the second DMA logic onto the programmable hardware element;
• and
• deploy the second graphical program to the controller;
• wherein the first graphical program and the second graphical program are executable to communicate via the DMA structure to cooperatively perform a specified task.