Detector in parallel with a logic component
AssigneeIntel Corporation
InventorItay Admon
Life of this patent
Estimating the term…
Abstract
One or more detectors are provided for processing input in parallel with a logic component receiving the same input. Apparatus described herein include one or more logic components that are configured to perform logical operations on an input vector, and one or more detectors that are configured to receive a portion of the input vector. The detector is further configured to perform detections on this portion of the input vector in parallel with the logical operation. Methods described herein include identifying a portion of the input vector, wherein the portion of the input vector appears an output of the logic component, and analyzing the portion of the vector in parallel with a logical operation performed by the logic component.
Claims15
Apparatus comprising:
- a processor communicatively coupled with a coder-decoder (codec) adapted to process data, wherein the processor comprises:
- a logic component configured to perform at least one logical operation on an input vector, wherein the logic component is operable in a plurality of selectable operating modes;
- and
- a detector configured to receive as input at least a portion of the input vector and to perform at least one detection on the portion of the input vector in parallel with the logical operation, wherein the detector comprises a multiplexer to receive a remainder of the input vector, and wherein the portion of the input vector is a common potion of the input vector to be output by the logic component when operating in selectable operating modes.
A computer-implemented method for communicating data between a processor and a coder-decoder (codec) comprising:
- storing, in a memory, instructions for performing the method for communicating data between a processor and a coder-decoder (codec), wherein the processor is communicatively coupled to the coder-decoder (codec);
- executing the instructions on a processor;
- according to the instructions being executed:
- identifying a portion of a vector input to a logic component, wherein the portion of the vector appears in an output of the logic component;
- and
- analyzing the portion of the vector in parallel with a logic operation performed by the logic component, wherein said analyzing the portion of the vector comprises determining whether bits in the portion of the vector are set to a logical-one value.
Apparatus comprising:
- a processor communicatively coupled with a coder-decoder (codec) adapted to process data, wherein the processor comprises:
- a logic component configured to perform at least one logical operation on an input vector;
- a detector configured to receive as in put at least a portion of the in put vector and to perform at least one detection on the portion of the input vector in parallel with the logical operation, wherein the detector comprises a multiplexer to receive a remainder of the input vector;
- and
- a further logic component configured to perform a further logic operation on the input vector, and wherein the detector includes:
- at least a first component that is configured to perform a first detection on the portion of the input vector in parallel with the logic operation;
- and
- at least a further component that is configured to perform at least a further detection on a further portion of the input vector in parallel with the further logic operation.
Dependencies are inferred from the claim text.