Gate-level netlist reduction for simulating target modules of a design
AssigneeLSI Corporation
InventorsMaurizio Spadari, Stefano Commodaro
Life of this patent
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Abstract
A method for analyzing a circuit design in preparation for a simulation. The method generally includes the steps of (A) marking each of a plurality of modules between a target module of the modules and a top module of the modules in a hierarchy of the circuit design as a first type by traversing upward through the hierarchy starting from the target module, (B) marking each of the modules as a second type where a parent module of the modules is marked as the first type by traversing downward through the hierarchy starting from the top module and (C) marking each of the modules as a third type where the parent module is not marked as the keep type by traversing downward through the hierarchy starting from the top module.
Claims21
A method for analyzing a circuit design in preparation for a simulation, comprising the steps of:
- (A) marking in a memory each of a plurality of modules between a target module of said modules and a top module of said modules inclusively in a hierarchy of said circuit design as a first type by traversing upward in said hierarchy starting from said target module;
- (B) marking in said memory each of said modules as a second type where a parent module of said modules is marked as said first type by traversing downward in said hierarchy starting from said top module;
- (C) marking in said memory each of said modules as a third type where said parent module is marked as one of (i) said second type and (ii) said third type by traversing downward in said hierarchy starting from said top module;
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- (D) generating a netlist of said circuit design in said memory, wherein (i) said first type designates said simulation in a full form, (ii) said second type designates said simulation in a black-box form and (iii) said third type designates a non-simulation form.
A storage medium for use in a computer, said storage medium recording a computer program, when executed said computer program comprising the steps of:
- (A) marking in a memory each of a plurality of modules between a target module of said modules and a top module of said modules inclusively in a hierarchy of a circuit design as a first type by traversing upward in said hierarchy starting from said target module;
- (B) marking in said memory each of said modules as a second type where a parent module of said modules is marked as said first type by traversing downward in said hierarchy starting from said top module;
- (C) marking in said memory each of said modules as a third type where said parent module is marked as one of (i) said second type and (ii) said third type by traversing downward in said hierarchy starting from said top module;
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- (D) generating a netlist of said circuit design in said memory, wherein (i) said first type designates a simulation in a full form, (ii) said second type designates said simulation in a black-box form and (iii) said third type designates a non-simulation form.
A method for reducing a full netlist of a circuit design in preparation for simulation, comprising the steps of:
- (A) generating a plurality of module netlists by parsing said full netlist among a plurality of modules in a hierarchy of said circuit design with a processor;
- (B) categorizing in a memory all of said modules as not analyzed;
- (C) categorizing in said memory a first one or more of said modules as a first type simulated in a full form;
- (D) categorizing in said memory a second one or more of said modules as a second type simulated in a black-box form;
- (E) categorizing in said memory a third one or more of said modules as a third type not simulated where a parent module is one of (i) said second type and (ii) said third type by traversing downward in said hierarchy starting from a top module;
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- (F) reducing each of said module netlists corresponding to said second type in said memory to said black-box form with said processor.
A storage medium for use in a computer, said storage medium recording a computer program, when executed said computer program comprising the steps of:
- (A) generating a plurality of module netlists by parsing a full netlist among a plurality of modules in a hierarchy of a circuit design;
- (B) categorizing all of said modules as not analyzed;
- (C) categorizing a first one or more of said modules as a first type simulated in a full form;
- (D) categorizing a second one or more of said modules as a second type simulated in a black-box form;
- (E) categorizing a third one or more of said modules as a third type not simulated where a parent module is one of (i) said second type and (ii) said third type by traversing downward in said hierarchy starting from a top module;
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- (F) reducing each of said module netlists corresponding to said second type to said black-box form.
A method for preparing a circuit design for a simulation, comprising the steps of:
- (A) categorizing in a memory a first one or more of a plurality of modules of said circuit design as a first type simulated in a full form;
- (B) categorizing in said memory a second one or more of said modules as a second type influencing said first type during said simulation;
- (C) categorizing in said memory a third one or more of said modules as a third type not influencing said first type during said simulation where a corresponding parent module of each of said third modules is one of (i) said second type and (ii) said third type;
- (D) reducing in said memory a full netlist of said circuit design by eliminating said modules having said third type;
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- (E) reducing in said memory said full netlist by representing said modules having said second type in a black-box form limited to a plurality of external ports.
A storage medium for use in a computer, said storage medium recording a computer program, when executed said computer program comprising the steps of:
- (A) categorizing a first one or more of a plurality of modules of a circuit design as a first type simulated in a full form;
- (B) categorizing a second one or more of said modules as a second type influencing said first type during a simulation;
- (C) categorizing a third one or more of said modules as a third type not influencing said first type during said simulation where a corresponding parent module of each of said third modules is one of (i) said second type and (ii) said third type;
- (D) reducing a full netlist of said circuit design by eliminating said modules having said third type;
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- (E) reducing said full netlist by representing said modules having said second type in a black-box form limited to a plurality of external ports.
Dependencies are inferred from the claim text.