Circuit for bit alignment in high speed multichannel data transmission

An apparatus for deskewing and aligning a plurality of parallel streams of data bits comprising:

• deskewing circuitry including:
• a multiphase clock generator having an operating frequency and generating a plurality of clock phases;
• a plurality of samplers, each sampler operatively coupled to the multiphase clock generator and to one of the streams of data bits;
• a plurality of phase selectors, each phase selector operatively coupled to one of the plurality of samplers;
• and
• a control logic circuit operatively coupled to each of the plurality of the samplers and to each of the plurality of the phase selectors;
• and
• an alignment circuit in operative communication with the deskewing circuitry, including:
• a plurality of aligners, each receiving successive pairs of primary data bits from the deskewing circuitry, wherein each aligner further includes:
• a first pair of flip-flop shifters generating a pair of data bits delayed by one cycle relative to the primary data bits;
• a second pair of flip-flop shifters generating a pair of data bits delayed by two cycles relative to the primary data bits;
• a third flip-flop shifter generating a data bit delayed by two and one half cycles relative to the primary data bits;
• a logic test circuit generating three control signals;
• and
• a single multiplexer operatively coupled to the plurality of flip-flop shifters and the logic test circuitry and operative under control of the three control signals, each directly coupled to the single multiplexer, to generate a pair of aligned data bits;
• and
• a control circuitry operatively coupled to each of the plurality of aligners.