Method and apparatus for memory efficient compressed domain video processing
AssigneeSeiko Epson Corporation
InventorsWilliam Chen, Vasudev Bhaskaran
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Abstract
A method for reducing the memory requirements for decoding a bit stream is provided. The method initiates with receiving a video bit stream. Then, a frame of the bit stream is decoded into a discrete cosine transform (DCT) domain representation. Next, non-zero coefficients of the DCT domain representation are identified. Then, a hybrid data structure is assembled. The hybrid data structure includes a fixed size array and a variable size overflow vector. Next, the non-zero coefficients of the DCT domain representation are inserted into the hybrid data structure. A computer readable media, a printed circuit board and a device configured to decode video data are also provided.
Claims23
A computer readable media having program instructions for reducing the memory requirements for decoding a video bit stream, the program instructions comprising instructions for:
- decoding a frame of the bit stream into a transform domain representation that comprises a first group of blocks, each storing a plurality of coefficients of the transform domain representation, at least some of the plurality of coefficients being non-zero coefficients;
- assembling a hybrid data structure including a fixed size array comprising a second group of blocks, each associated with a respective one of the blocks in the first group of blocks, and a variable size overflow vector associated with the frame;
- and
- inserting the non-zero coefficients of the transform domain representation into the hybrid data structure, wherein each block of the second group of blocks stores at least some non-zero coefficients from the corresponding block of the first group of blocks and the variable size overflow vector stores the remaining non-zero coefficients from the corresponding block.
A computer readable media having program instructions for decoding a frame of video data within a compressed bit stream, the program instructions comprising instructions for:
- decoding the frame into a transform domain representation that comprises a first group of blocks, each storing a plurality of coefficients of the transform domain representation, at least some of the plurality of coefficients being non-zero coefficients;
- defining a hybrid data structure comprising a second group of blocks, each associated with a respective one of the blocks in the first group of blocks, and a variable size overflow vector associated with the frame;
- storing data associated with the transform domain representation in the hybrid data structure, such that non-zero coefficients from a particular block of the first group of blocks are stored in the associated block of the second group of blocks until a capacity of the associated block is reached, and then any remaining non-zero coefficients from the particular block are stored in the variable size overflow vector;
- performing inverse motion compensation on the data associated with the transform domain representation in the compressed domain;
- and
- after performing the inverse motion compensation on the data, decompressing the data for display.
A computer readable media having program instructions for rearranging low rate bit stream data for storage into a hybrid data structure, comprising:
- program instructions for identifying non-zero transform coefficients associated with a coded block of a frame of data;
- program instructions for arranging the non-zero transform coefficients into a fixed size array;
- program instructions for determining if a quantity of the non-zero transform coefficients exceed a capacity of the fixed size array;
- program instructions for storing the non-zero transform coefficients exceeding the capacity of the fixed size array in a variable size overflow vector;
- and
- program instructions for translating the non-zero transform coefficients from a compressed domain to a spatial domain.
A device configured to display a video image, comprising:
- a central processing unit (CPU);
- a random access memory (RAM);
- a display screen configured to present an image;
- decoder circuitry configured to transform a video bit stream into a transform domain representation that comprises a first group of blocks, each storing a plurality of coefficients of the transform domain representation, at least some of the plurality of coefficients being non-zero coefficients, the decoder circuitry capable of arranging non-zero transform coefficients of the transform domain representation in a hybrid data structure in a memory associated with the decoder circuitry, the decoder circuitry including circuitry for selectively applying a hybrid factorization/integer approximation technique during inverse motion compensation;
- and
- a bus in communication with the CPU, the RAM, the display screen and the decoder circuitry;
- wherein the hybrid data structure comprises a second group of blocks, each associated with a respective one of the blocks in the first group of blocks and each of which stores at least some non-zero coefficients from the corresponding block of the first group of blocks, and a variable size overflow vector that stores the remaining non-zero coefficients from the corresponding block.
Dependencies are inferred from the claim text.