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US 7,606,110 B2Granted
Memory module, memory unit, and hub with non-periodic clock and methods of using the same
AssigneeSamsung Electronics Co., Ltd.
InventorsYou-Keun Han, Hui-Chong Shin, Seung-Jin Seo, Byung-Se So, Young-Man Ahn, Seung-Man Shin, Jung-Kuk Lee, Ho-Suk Lee
Life of this patent
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Abstract
A memory module, a memory unit, and a hub with a non-periodic clock and methods for using the same. An example memory module may include a phased locked loop, receiving an external, periodic clock and generating one or more internal periodic clocks and a plurality of memory units, receiving one of the internal periodic clocks or a non-periodic clock from an external source.
Claims20
A memory module comprising:
- a phased locked loop receiving an external, periodic clock and generating one or more internal periodic clocks;
- and
- a plurality of memory units selectively receiving one of the internal periodic clocks or a first non-periodic clock from an external source, the first non-periodic clock being a clock having an irregular period or irregular duty cycle, and each of the plurality of memory units including,
- a mode set circuit receiving an input signal and outputting a mode signal, and
- a clock selection circuit receiving the received periodic clock and the non-periodic clock and outputting either the periodic clock or the non-periodic clock depending on the mode signal.
2 more elements
A memory module comprising:
- a phased locked loop receiving an external, periodic clock and generating one or more internal periodic clocks;
- a plurality of memory units selectively receiving one of the internal periodic clocks or a first non-periodic clock from an external source, the first non-periodic clock being a clock having an irregular period or irregular duty cycle;
- a register receiving one of the internal periodic clocks, control and address information from the external source and supplying the control and address information to the plurality of memory units in synchronization with the received internal periodic clock;
- and
- a clock selection circuit, including a memory clock selection circuit, receiving the first non-periodic clock, the one of the internal periodic clocks and a mode select signal, the memory clock selection circuit providing one of the internal periodic clocks or the first non-periodic clock to the plurality of memory units depending on the mode select signal.
2 more elements
A memory module comprising:
- a phased locked loop receiving an external, periodic clock and generating one or more internal periodic clocks;
- a plurality of memory units selectively receiving one of the internal periodic clocks or a first non-periodic clock from an external source, the first non-periodic clock being a clock having an irregular period or irregular duly cycle;
- a register receiving control and address information from an external source and supplying the control and address information to the plurality of memory units;
- and
- a clock selection circuit including,
- a memory clock selection circuit receiving the first non-periodic clock, the one of the internal periodic clocks and a first mode select signal, the memory clock selection circuit providing one of the internal periodic clocks or the first non-periodic clock to the plurality of memory units depending on the first mode select signal, and
- a register clock selection circuit receiving the first non-periodic clock, the one of the internal periodic clocks and a second mode select signal, the register clock selection circuit providing one of the internal periodic clocks or the first non-periodic clock to the register depending on the second mode select signal.
4 more elements
A memory module comprising:
- a phased locked loop receiving an external, periodic clock and generating one or more internal periodic clocks;
- a plurality of memory units selectively receiving one of the internal periodic clocks or a first non-periodic clock from an external source, the first non-periodic clock being a clock having an irregular period or irregular duty cycle;
- a register receiving control and address information from an external source and supplying the control and address information to the plurality of memory units;
- and
- a clock selection circuit including,
- a memory clock selection circuit receiving the first non-periodic clock, the one of the internal periodic clocks and a first mode select signal, the memory clock selection circuit providing one of the internal periodic clocks or the first non-periodic clock to the plurality of memory units depending on the first mode select signal, and
- a register clock selection circuit receiving a second non-periodic clock, the one of the internal periodic clocks and a second mode select signal, the register clock selection circuit providing one of the internal periodic clocks or the second non-periodic clock to the register depending on the second mode select signal.
4 more elements
A hub on a memory module, comprising:
- a phased locked loop receiving an external, periodic clock and generating one or more internal periodic clocks;
- a set register receiving a mode set signal and generating one or more control signals;
- a memory interface register receiving memory information and supplying the memory information to a plurality of memory units;
- and
- a clock selection circuit receiving a first non-periodic clock, the one of the internal periodic clocks and the one or more control signals, and providing the one of the internal periodic clocks or the first non-periodic clock to the plurality of memory units and the memory interface register depending on the one or more control signals, wherein
- the first non-periodic clock is a clock having an irregular period or irregular duty cycle.
3 more elements
A memory unit, comprising:
- a first input pin receiving a periodic clock in a normal mode;
- a second input pin receiving a non-periodic clock in a test mode, the non-periodic clock being a clock having an irregular period or irregular duty cycle;
- a clock selection circuit, receiving the periodic clock and the non-periodic clock and outputting either the periodic clock or the non-periodic clock, depending on a mode selection signal;
- and
- a clock buffer receiving either the periodic clock or the non-periodic clock from the clock select circuit and outputting an internal clock.
2 more elements
Dependencies are inferred from the claim text.