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US 7,606,107 B2Granted
Memory cell, read device for memory cell, memory assembly, and corresponding method
AssigneeInfineon Technologies AG
InventorsPeter Huber, Yannick Martelloni, Thomas Nirschl, Martin Ostermayr
Life of this patent
Estimating the term…
Abstract
A memory cell includes transistors and two read ports. Each read port is configured to be connected to a read line. The memory cell is configured such that in a read operation of the memory cell an information stored in the memory cell is readable by a differential reading including an evaluation of an electric current between the two read ports.
Claims31
A memory cell, comprising:
- transistors;
- and
- two read ports, each read port configured to be connected to a read line, wherein the memory cell is configured such that in a read operation of the memory cell an information stored in the memory cell is readable by a differential reading including an evaluation of an electric current between the two read ports, wherein the memory cell is configured such that in a read operation, for a case that the memory cell stores a binary 0 or a 1 respectively, the memory cell sets an electrical connection between the two read ports to low impedance, in comparison to a case that the memory cell stores a binary 1 or a 0 respectively.
A memory cell, comprising:
- a first read port;
- a second read port;
- a first transistor having a first terminal operatively connected to the first read port, a second terminal, and a control input;
- a second transistor having a first terminal operatively connected to the second terminal of the first transistor, a second terminal operatively connected to the second port, and a control input;
- a third transistor having a first terminal and second terminal operatively connected to the control input of the second transistor;
- a write port operatively connected to the first terminal of the third transistor;
- a write control terminal operatively connected to the control input of the first transistor;
- and
- a read control terminal operatively connected to the control input of the first transistor.
6 more elements
A memory assembly configured to read and write information, comprising:
- two read lines;
- one write line;
- at least two memory cells, each of the memory cells comprising:
- a first read port operatively connected to one of the two read lines;
- a second read port operatively connected to the other one of the two read lines;
- a first transistor having a first terminal operatively connected to the first read port, a second terminal, and a control input;
- a second transistor having a first terminal operatively connected to the second terminal of the first transistor, a second terminal operatively connected to the second port, and a control input;
- a third transistor having a first terminal and second terminal operatively connected to the control input of the second transistor;
- a write port operatively connected the write line and to the first terminal of the third transistor;
- a write control terminal operatively connected to the control input of the first transistor;
- and
- a read control terminal operatively connected to the control input of the first transistor;
- and
- an arrangement configured to activate at least one of the at least two memory cells to read or write the information stored therein.
11 more elements
A read device, comprising:
- transistors;
- two input terminals;
- and
- one output terminal;
- means for reading a one-bit information via a current that flows between the two input terminals;
- means for providing the one-bit information via the output terminal;
- and
- means for setting the read device's own operating point by setting the potential of the two input terminals.
5 more elements
A read device comprising:
- two input terminals;
- one output terminal;
- a first transistor of a first conduction type including:
- a first terminal;
- a second terminal;
- and
- a control input;
- a second transistor of the first conduction type including:
- a first terminal operatively connected to the first terminal of the first transistor and a first supply voltage;
- a second terminal;
- and
- a control input;
- a third transistor of a second conduction type including:
- a first terminal;
- a second terminal;
- and
- a control input;
- a fourth transistor of the second conduction type including:
- a first terminal operatively connected to the second terminal of the first transistor and the output terminal of the read device;
- a second terminal;
- and
- a control input operatively connected to the control input of the third transistor and the first supply voltage;
- and
- a fifth transistor of the second conduction type including:
- a first terminal operatively connected to a second one of the two input terminals of the read device, the control input of the first transistors, the control input of the second transistor, and the second terminal of the third transistor;
- a second terminal operatively connected the second terminal of the fourth transistor and a second supply voltage;
- and
- a control input operatively connected to a first one of the two input terminals of the read device, the second terminal of the second transistor, and the first terminal of the third transistor.
25 more elements
A memory assembly comprising:
- memory cells, each memory cell including transistors and two read ports;
- at least one read device including transistors, two input terminals, and one output terminal, the at least one read device configured to read a one-bit information via a current that flows between the two input terminals, provide the one-bit information via the output terminal, and set its own operating point by setting the potential of the two input terminals;
- a first line connected to a first one of the two read ports of each memory cell and to one of the two input terminals of the read device;
- and
- a second line connected to a second one of the two read ports of each memory cell and to the other one of the two input terminals of the read device.
2 more elements
A method of operating a memory cell, the method comprising:
- reading information stored in the memory cell with a differential read operation including evaluating an electric current between two read ports of the memory cell;
- and
- during the reading, connecting only a well contact and a substrate contact of the memory cell with a supply voltage.
Dependencies are inferred from the claim text.