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US 7,606,105 B2Granted
Deep power down mode control circuit
AssigneeHynix Semiconductor Inc.
InventorShin Ho Chu
Life of this patent
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Abstract
A deep power down mode control circuit is provided. The deep power down mode control circuit includes a deep power down signal generator for outputting a deep power down signal in response to a burst command signal and a clock enable signal, and a deep power down delay controller for delaying the deep power down signal for a predetermined delay time, and outputting the delayed signal.
Claims11
A deep power down mode control circuit comprising:
- a deep power down signal generator configured to output a first deep power down signal in response to a burst command signal and a clock enable signal;
- and
- a deep power down delay controller configured to receive the first deep power down signal and generate a second deep power down signal, wherein the second deep power down signal is enabled to activate a deep power down mode and an enable period of the second deep power down signal is larger than an enable period of the first deep power down signal.
A deep power down mode control circuit comprising:
- an inverter configured to drive an output node in response to a first deep power down signal;
- a latch configured to latch a signal outputted from the output node in response to the power up signal, and output a second deep power down signal;
- an internal delay configured to delay the second deep power down signal for a predetermined period and output a deep power down delay signal;
- and
- a switch configured to control a driving of the inverter in response to the power up signal and the deep power down delay signal.
2 more elements
Dependencies are inferred from the claim text.