Semiconductor memory device and electric power supply method

A semiconductor device comprising:

• a first and second memory cell array each including a plurality of electrically reprogrammable memory cells arranged in the form of a matrix, the first memory cell array having a larger capacity than the second memory cell array:
• a plurality of word lines and a plurality of bit lines connected to said plurality of memory cells;
• a data program and read control section including a plurality of decoders for read or erasure with respect to a corresponding memory cell among the plurality of memory cells, selecting a corresponding word line and a corresponding bit line among said plurality of word lines and said plurality of bit lines and applying a voltage to said corresponding word line and said corresponding bit line when performing data programming;
• and
• power supply circuit for supplying power to said data program and read control section, wherein when said power supply circuit is to supply power to said second memory cell array, an output terminal of said power supply circuit is electrically connected to at least one of said plurality of decoders connected to said first memory cell array,
• wherein said first memory cell array is a main part memory cell array and said second memory cell array is a ROM memory cell array.

A semiconductor device comprising:

• a first and second memory cell array each including a plurality of electrically reprogrammable memory cells arranged in the form of a matrix, the first memory cell array having a larger capacity than the second memory cell array;
• a plurality of word lines and a plurality of bit lines connected to said plurality of memory ce1ls;
• a data program and read control section including a plurality of decoders for read or erasure with respect to a corresponding memory cell among the plurality of memory cells, selecting a corresponding word line and a corresponding bit line among said plurality of word lines and said plurality of bit lines and applying a voltage to said corresponding word line and said corresponding bit line when performing data programming;
• and
• a power supply circuit for supplying power to said data program and read control section, wherein when said power supply circuit is to supply power to said second memory cell array, an output terminal of said power supply circuit is electrically connected to at least one of said plurality of decoders connected to said first memory cell array,
• wherein said power supply circuit includes a regulator for cell gate voltage for controlling a voltage to be supplied to a gate of said corresponding memory cell among said plurality of memory cells, and a read voltage boost circuit for controlling a voltage to be supplied to a gate of said corresponding memory cell among said plurality of memory cells for reading data from said corresponding memory cell.

A semiconductor device comprising:

• a first and a second memory cell array each including a plurality of electrically reprogrammable memory cells arranged in the form of a matrix, said first memory cell array having a larger capacity than said second memory cell array;
• a plurality of word lines and a plurality of bit lines connected to said plurality of memory cells;
• a data program and read control section including a plurality of decoders for read or erasure with respect to a corresponding memory cell among said plurality of memory cells, selecting a corresponding word line and a corresponding bit line among the plurality of word lines and the plurality of bit lines and applying a voltage to the corresponding word line and said corresponding bit line when performing data programming;
• a power supply circuit for supplying power to said data program and read control section, wherein when said power supply circuit is to supply power to said second memory cell array, an output terminal of said power supply circuit is electrically connected to at least one of said plurality of decoders connected to said first memory cell array;
• and
• a decoder selecting circuit for, when said power supply circuit is to supply power to said second memory cell array, selecting a corresponding decoder among said plurality of decoders connected to said first memory cell array.

An electric power supply method for a semiconductor device, said semiconductor device comprising:

• a first and a second memory cell array each including a plurality of electrically reprogrammable memory cells arranged in the form of a matrix, said first memory cell array having a larger capacity than said second memory cell array;
• a plurality of word lines and a plurality of bit lines connected to said plurality of memory cells;
• a data program and read control section including a plurality of decoders for read or erasure with respect to a corresponding memory cell among said plurality of memory cells, selecting a corresponding word line and a corresponding bit line among said plurality of word lines and said plurality of bit lines and applying a voltage to said corresponding word line and said corresponding bit line when performing data programming;
• and
• a power supply circuit for supplying power to said data program and read control section;
• said method comprising:
• electrically connecting an output terminal of said power supply circuit to at least one of said plurality of decoders connected to said first memory cell array and electrically disconnecting said one of said plurality of decoders connected to said first memory cell array from said corresponding word line when said power supply circuit is to supply power to said second memory cell array.

An electric power supply method for a semiconductor device, said semiconductor device comprising:

• a first and a second memory cell array each including a plurality of electrically reprogrammable memory cells arranged in the form of a matrix, said first memory cell array having a larger capacity than said second memory cell array;
• a plurality of word lines and a plurality of bit lines connected to said plurality of memory cells;
• a data program and read control section including a plurality of decoders for read or erasure with respect to a corresponding memory cell among said plurality of memory cells, selecting a corresponding word line and a corresponding bit line among said plurality of word lines and said plurality of bit lines and applying a voltage to said corresponding word line and said corresponding bit line when performing data programming;
• and
• a power supply circuit for supplying power to said data program and read control section;
• said method comprising:
• electrically connecting an output terminal of said power supply circuit to at least one of said plurality of decoders connected to said first memory cell array when said power supply circuit is to supply power to said second memory cell array,
• wherein said first memory cell array is a main part memory cell array and said second memory cell array is a ROM memory cell array.

An electric power supply method for a semiconductor device, said semiconductor device comprising:

• a first and a second memory cell array each including a plurality of electrically reprogrammable memory cells arranged in the form of a matrix, said first memory cell array having a larger capacity than said second memory cell array;
• a plurality of word lines and a plurality of bit lines connected to said plurality of memory cells;
• a data program and read control section including a plurality of decoders for read or erasure with respect to a corresponding memory cell among said plurality of memory cells, selecting a corresponding word line and a corresponding bit line among said plurality of word lines and said plurality of bit lines and applying a voltage to said corresponding word line and said corresponding bit line when performing data programming;
• and
• a power supply circuit for supplying power to said data program and read control section;
• said method comprising:
• electrically connecting an output terminal of said power supply circuit to at least one of said plurality of decoders connected to said first memory cell array when said power supply circuit is to supply power to said second memory cell array,
• wherein said power supply circuit includes a regulator for cell gate voltage for controlling a voltage to be supplied to a gate of said corresponding memory cell among said plurality of memory cells, and a read voltage boost circuit for controlling a voltage to be supplied to a gate of said corresponding memory cell among said plurality of memory cells for reading data from said corresponding memory cell.