Circuit and method for controlling a clock synchronizing circuit for low power refresh operation
AssigneeMicron Technology, Inc.
InventorsAaron M. Schoenfeld, Ross E. Dermott
Life of this patent
Estimating the term…
Abstract
A method and apparatus is provided for idling a clock synchronizing circuit during at least a portion of time during execution of a refresh operation in a memory device. In a memory device receiving an external clock signal, a method and apparatus for executing a refresh operation is provided that includes initiating at least one refresh operation in the memory device, and ceasing generation of an internal clock signal timed with respect to the external clock signal for at least a portion of the time in which at least one refresh operation takes to complete.
Claims17
A method of conserving power in a memory device, comprising:
- pausing an operation of a portion of the memory device responsive to at least one of a plurality of control signals having an active value, one of the plurality of control signals a control signal indicative of a refresh operation;
- and
- resuming the paused operation of the portion of the memory device responsive to each of the plurality of control signals having an inactive value.
A method of conserving power in a memory device during a non-power down state, comprising:
- determining an operation is to be performed;
- temporarily idling a circuitry of the memory device not utilized for the operation for at least a portion of time during which the operation is performed;
- and
- adjusting timing of the circuitry after it was temporarily idled for changes in timing in the circuitry that occurred when the circuitry was temporarily idled.
A method of conserving power in a memory device, comprising:
- pausing an operation of a portion of the memory device responsive to at least one of a plurality of control signals having an active value, one of the plurality of control signals a control signal having an active value responsive to N occurrences of a triggering event, N being a positive integer greater than 1;
- and
- resuming the paused operation of the portion of the memory device responsive to each of the plurality of control signals having an inactive value.
A method of conserving power in a memory device during a non-power down state, comprising:
- determining a refresh operation is to be performed;
- and
- temporarily idling a circuitry of the memory device not utilized for the operation for at least a portion of time during which the operation is performed.
Dependencies are inferred from the claim text.