Array sense amplifiers, memory devices and systems including same, and methods of operation

An amplifier for sensing a differential voltage comprising:

• a precharge switch coupled to a pair of output terminals and configured to precharge the pair of output terminals to the same voltage level;
• a first pair of transistors cross-coupled to each other and to the pair of output terminals respectively, each transistor of the first pair operable to couple one of the pair of output terminals to a first voltage;
• a second pair of transistors cross-coupled to each other and to the pair of output terminals respectively, each transistor of the second pair operable to couple one of the pair of output terminals to a second voltage;
• and
• a resistance circuit coupled to the second pair of transistors and to a ground source, the resistance circuit configured to reduce the gain of the second pair of transistors.

A sense amplifier for sensing a differential voltage between a pair of complementary digit lines comprising:

• a first sense line and a second sense line complementary to the first sense line;
• a precharge NMOS transistor coupled to the first and second sense lines, and further having a gate configured to receive a precharge control signal for equilibrating the first and second sense lines to the same voltage level;
• a first sense amplifier stage comprising a pair of PMOS transistors cross-coupled to the first and second sense lines respectively, and further being coupled to a first voltage supply, the pair of PMOS transistors operable to amplify the first sense line towards the first voltage supply;
• and
• a second sense amplifier stage comprising:
• a first pair of NMOS transistors cross-coupled to the first and second sense lines respectively, and further coupled to the pair of PMOS transistors;
• a second pair of NMOS transistors coupled to the first pair of NMOS transistors and to a second voltage supply, and further having its gates coupled to each other to receive a latch control signal, the second pair of NMOS transistors operable to adjust the gain of the second sense amplifier stage responsive to the latch control signal, wherein the first and second pair of NMOS transistors are further operable to amplify the second sense line towards the second voltage supply;
• and
• a third pair of NMOS transistors, each transistor correspondingly coupled to each of the first pair of NMOS transistors and to the second voltage supply, the third pair of NMOS transistors configured to increase the signal drive of the second sense amplifier stage.

A memory device, comprising:

• an address bus;
• a control bus;
• a data bus;
• an address decoder coupled to the address bus;
• a read/write circuit coupled to the data bus;
• a control circuit coupled to the control bus;
• an array of memory cells coupled to the address decoder, control circuit, and read/write circuit;
• and
• a plurality of sense amplifier coupled to the array of memory cells, each sense amplifier comprising:
• a first input/output (“I/O”) node and a second I/O node complementary to the first I/O node;
• a first amplifier stage operable to couple the first I/O node to a first voltage and amplify a first I/O node signal to the first voltage;
• a second amplifier stage operable to couple the second I/O node to a second voltage and amplify a second I/O node signal to the second voltage;
• and
• a resistance circuit coupled to the second amplifier stage and configured to reduce the gain of the second amplifier stage to slow the rate of amplification of the second I/O node signal, the resistance circuit comprising two NMOS transistors configured to provide a resistance, the two NMOS transistors having gates coupled together to receive a control signal to provide the resistance.

A computer system, comprising:

• a data input device;
• a data output device;
• a processor coupled to the data input and output devices;
• and
• a memory device coupled to the processor, comprising:
• an address bus;
• a control bus;
• a data bus;
• an address decoder coupled to the address bus;
• a read/write circuit coupled to the data bus;
• a control circuit coupled to the control bus;
• an array of memory cells coupled to the address decoder, control circuit, and read/write circuit;
• and
• a plurality of sense amplifier coupled to the array of memory cells, each sense amplifier comprising:
• a first input/output (“I/O”) node and a second I/O node complementary to the first I/O node;
• a first amplifier stage operable to couple the first I/O node to a first voltage and amplify a first I/O node signal to the first voltage;
• a second amplifier stage operable to couple the second I/O node to a second voltage and amplify a second I/O node signal to the second voltage;
• and
• a resistance circuit coupled to the second amplifier stage and configured to reduce the gain of the second amplifier stage to slow the rate of amplification of the second I/O node signal, the resistance circuit comprising two NMOS transistors configured to provide a resistance, the two NMOS transistors having gates coupled together to receive a control signal to provide the resistance.

A method of sensing a differential voltage between first and second digit lines that are complementary, the method comprising:

• activating a first amplifier in response to a received signal on the first digit line to drive a signal on the second digit line;
• reducing the gain of the first amplifier to slow the amplification of the signal on the second digit line;
• activating a second amplifier to inversely amplify the received signal on the first digit line;
• and
• generating complementary output signals indicative of the amplification of signals on the first and second digit lines.

A method of sensing a differential voltage between a pair of complementary digit lines comprising:

• precharging the pair of complementary digit lines to the same signal level;
• receiving a first signal on a first digit line of the pair of digit lines;
• amplifying a second signal on a second digit line of the pair of digit lines;
• applying a resistance to slow the amplification of the second signal;
• amplifying the first signal received on the first digit line to a polarity opposite the polarity of the second signal and in response to the amplification of the second signal on the second digit line;
• and
• outputting complementary digital signals on each of the respective digit lines.

A sense amplifier comprising:

• a first input/output (“I/O”) node and a second I/O node complementary to the first I/O node;
• a first amplifier stage operable to couple the first I/O node to a first voltage and amplify a first I/O node signal to the first voltage;
• a second amplifier stage operable to couple the second I/O node to a second voltage and amplify a second I/O node signal to the second voltage, the second stage comprising cross-coupled NMOS transistors;
• and
• a resistance circuit coupled to the second amplifier stage and configured to reduce the gain of the second amplifier stage to slow the rate of amplification of the second I/O node signal.

A sense amplifier comprising:

• a first input/output (“I/O”) node and a second I/O node complementary to the first I/O node;
• a first amplifier stage operable to couple the first I/O node to a first voltage and amplify a first I/O node signal to the first voltage;
• a second amplifier stage operable to couple the second I/O node to a second voltage and amplify a second I/O node signal to the second voltage;
• a resistance circuit coupled to the second amplifier stage and configured to reduce the gain of the second amplifier stage to slow the rate of amplification of the second I/O node signal;
• and
• an equilibrium circuit coupled to the first and second I/O nodes, and configured to receive a control signal for precharging the first and second I/O nodes to the same voltage.

A memory device, comprising:

• an address bus;
• a control bus;
• a data bus;
• an address decoder coupled to the address bus;
• a read/write circuit coupled to the data bus;
• a control circuit coupled to the control bus;
• an array of memory cells coupled to the address decoder, control circuit, and read/write circuit;
• and
• a plurality of sense amplifier coupled to the array of memory cells, each sense amplifier comprising:
• a first input/output (“I/O”) node and a second I/O node complementary to the first I/O node;
• a first amplifier stage operable to couple the first I/O node to a first voltage and amplify a first I/O node signal to the first voltage;
• a second amplifier stage operable to couple the second I/O node to a second voltage and amplify a second I/O node signal to the second voltage, the second amplifier stage comprising cross-coupled NMOS transistors;
• and
• a resistance circuit coupled to the second amplifier stage and configured to reduce the gain of the second amplifier stage to slow the rate of amplification of the second I/O node signal.

A memory device, comprising:

• an address bus;
• a control bus;
• a data bus;
• an address decoder coupled to the address bus;
• a read/write circuit coupled to the data bus;
• a control circuit coupled to the control bus;
• an array of memory cells coupled to the address decoder, control circuit, and read/write circuit;
• and
• a plurality of sense amplifier coupled to the array of memory cells, each sense amplifier comprising:
• a first input/output (“I/O”) node and a second I/O node complementary to the first I/O node;
• a first amplifier stage operable to couple the first I/O node to a first voltage and amplify a first I/O node signal to the first voltage;
• a second amplifier stage operable to couple the second I/O node to a second voltage and amplify a second I/O node signal to the second voltage;
• a resistance circuit coupled to the second amplifier stage and configured to reduce the gain of the second amplifier stage to slow the rate of amplification of the second I/O node signal;
• and
• an equilibrium circuit coupled to the first and second I/O nodes, and configured to receive a control signal for precharging the first and second I/O nodes to the same voltage.

A computer system, comprising:

• a data input device;
• a data output device;
• a processor coupled to the data input and output devices;
• and
• a memory device coupled to the processor, comprising:
• an address bus;
• a control bus;
• a data bus;
• an address decoder coupled to the address bus;
• a read/write circuit coupled to the data bus;
• a control circuit coupled to the control bus;
• an array of memory cells coupled to the address decoder, control circuit, and read/write circuit;
• and
• a plurality of sense amplifier coupled to the array of memory cells, each sense amplifier comprising:
• a first input/output (“I/O”) node and a second I/O node complementary to the first I/O node;
• a first amplifier stage operable to couple the first I/O node to a first voltage and amplify a first I/O node signal to the first voltage;
• a second amplifier stage operable to couple the second I/O node to a second voltage and amplify a second I/O node signal to the second voltage, the second amplifier stage comprising cross-coupled NMOS transistors;
• and
• a resistance circuit coupled to the second amplifier stage and configured to reduce the gain of the second amplifier stage to slow the rate of amplification of the second I/O node signal.

A computer system, comprising:

• a data input device;
• a data output device;
• a processor coupled to the data input and output devices;
• and
• a memory device coupled to the processor, comprising:
• an address bus;
• a control bus;
• a data bus;
• an address decoder coupled to the address bus;
• a read/write circuit coupled to the data bus;
• a control circuit coupled to the control bus;
• an array of memory cells coupled to the address decoder, control circuit, and read/write circuit;
• and
• a plurality of sense amplifier coupled to the array of memory cells, each sense amplifier comprising:
• a first input/output (“I/O”) node and a second I/O node complementary to the first I/O node;
• a first amplifier stage operable to couple the first I/O node to a first voltage and amplify a first I/O node signal to the first voltage;
• a second amplifier stage operable to couple the second I/O node to a second voltage and amplify a second I/O node signal to the second voltage;
• a resistance circuit coupled to the second amplifier stage and configured to reduce the gain of the second amplifier stage to slow the rate of amplification of the second I/O node signal;
• and
• an equilibrium circuit coupled to the first and second I/O nodes, and configured to receive a control signal for precharging the first and second I/O nodes to the same voltage.