Data strobe signal generator for generating data strobe signal based on adjustable preamble value and semiconductor memory device with the same
AssigneeHynix Semiconductor Inc.
InventorYong Suk Joo
Life of this patent
Estimating the term…
Abstract
A data strobe signal generator includes a control unit, a pulse delay unit, a clock generator, and a data strobe output unit. The control unit generates a CAS latency signal and a preamble signal. The pulse delay unit delays a pulse signal for predetermined time and outputs a delayed pulse signal. The clock generator outputs a control clock signal. The data strobe output unit outputs a data strobe signal. The data strobe signal generator and the semiconductor memory device having the same generate a data strobe signal based on an adjustable preamble value, thereby ensuring the stabilized data output operation of a high-speed memory device.
Claims30
A data strobe signal generator, comprising:
- a control unit for generating a column address strobe (CAS) latency signal and a preamble signal in response to a mode register set signal, an extended mode register set signal and address signals;
- a pulse delay unit for delaying a pulse signal for a predetermined time and outputting a delayed pulse signal in response to the CAS latency signal and the preamble signal;
- a clock generator for outputting a control clock signal in response to the CAS latency signal and the preamble signal;
- and
- a data strobe output unit for outputting a data strobe signal in response to the delayed pulse signal and the control clock signal.
A synchronous semiconductor memory device, comprising:
- an internal core circuit having a memory cell array;
- at least one data output circuit for outputting output data received from the internal core circuit to an external device via at least one data input/output pin;
- and
- a data strobe signal generator for generating a data strobe signal in response to a mode register set signal, an extended mode register set signal, address signals and an internal clock signal,
- wherein the data strobe signal generator comprises:
- a control unit for generating a column address strobe (CAS) latency signal and a preamble signal in response to the mode register set signal, the extended mode register set signal and address signals;
- a pulse delay unit for delaying a pulse signal for predetermined time and outputting a delayed pulse signal, in response to the CAS latency signal and the preamble signal;
- a clock generator for outputting a control clock signal in response to the CAS latency signal and the preamble signal;
- and
- a data strobe output unit for outputting a data strobe signal in response to the delayed pulse signal and the control clock signal.
Dependencies are inferred from the claim text.