Erase verifying method of NAND flash memory device
AssigneeHynix Semiconductor Inc.
InventorJu Yeab Lee
Life of this patent
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Abstract
In an erase verifying method of a NAND flash memory device, a power supply voltage (Vcc) is applied to a second bit line while precharging a first bit line to a first positive voltage. Select transistors are turned on, and a ground voltage is applied to word lines of memory cell transistors. A second positive voltage is applied to source lines to which sources of the select transistors and the memory cell transistors are connected. An erased state of the memory cell transistor is verified according to whether charges accumulated in the first bit line are discharged.
Claims17
A method for operating a flash memory device, the method comprising:
- performing an erase operation on memory cells in first and second cell strings, the first cell string including a first drain select transistor, a plurality of first memory cells, and a first source select transistor, which are connected in series, the first drain select transistor being connected to a first bit line, the first source select transistor being connected to a common source line;
- applying a power supply voltage (Vcc) to the second bit line while precharging the first bit line to a first positive voltage;
- turning on the first drain and source select transistors;
- applying a ground voltage to word lines of the first memory cells;
- applying a second positive voltage to the common source line;
- and
- verifying whether the memory cells have been erased properly.
A method for operating a flash memory device, the method comprising:
- performing an erase operation on a plurality of cell strings;
- and
- performing an erase verification on a selected cell string, the selected cell string including a drain select transistor, a plurality of memory cells, and a source select transistor, which are connected in series, the drain select transistor being connected to a bit line, the source select transistor being connected to a common source line, the erase verification step includes:
- precharging the bit line to a first positive voltage,
- turning on the select drain and source transistors,
- applying a ground voltage to word lines of the memory cell transistors,
- applying a second positive voltage to the common source line, and
- verifying whether the memory cell transistors have been erased properly.
Dependencies are inferred from the claim text.