Non-volatile memory with reduced erase/write cycling during trimming of initial programming voltage

A non-volatile memory comprising:

• an array of memory cells that is organized into erasable blocks, each erasable block containing a block of word lines for accessing memory cells that are erasable together, and each word line containing at least one page of memory cells that are programmable together;
• a designated sample of pages representative of the given page within a block;
• an associated programming voltage for programming each page of the sample, the associated programming voltage having a staircase waveform with an associated initial value and a predetermined number of steps;
• a built-in self testing module for determining the associated initial value for a given page, said module providing memory operations including:
• (a) erasing the block containing the sample of pages;
• (b) determining for every page in the sample if the page is programmed to a target pattern using the associated programming voltage with the associated initial value;
• and if programmed, excluding the page from further processing after accumulating the associated initial value as part of a gathered statistics, otherwise, incrementing the associated initial value by a predetermined step;
• (c) repeating (a) to (b) until each of the sample of pages has either been program-verified or been programmed with the associated programming voltage incremented to a predetermined maximum voltage;
• and
• (d) providing the gathered statistic for computing an average initial value for the sample and for deriving a starting programming voltage for the page based on the average initial value of the sample.