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US 7,606,075 B2Granted
Read operation for NAND memory
AssigneeMicron Technology, Inc.
InventorsSeiichi Aritome, Akira Goda
Life of this patent
Estimating the term…
Abstract
Non-volatile memory devices utilizing a NAND architecture are adapted to perform read operations where a first potential is supplied to source lines associated with a selected block of an array of memory cells and a second, different, potential is supplied to other source lines not associated with that block. By supplying a different potential to source lines of unselected blocks, current leakage can be mitigated.
Claims35
A method of performing a read operation on a target memory cell of a non-volatile memory device having at least two strings of series-coupled non-volatile memory cells, the method comprising:
- applying a first potential to a bit line selectively coupled to a string of series-coupled non-volatile memory cells containing the target memory cell;
- applying a second potential to a source line selectively coupled to the string of series-coupled non-volatile memory cells containing the target memory cell;
- applying a third potential to one or more source lines selectively coupled to the bit line and not selectively coupled to the string of series-coupled non-volatile memory cells containing the target memory cell, wherein the third potential has a value different than the second potential and wherein the third potential is not a ground potential of the memory device;
- and
- reading a data value of the target memory cell from a string of non-volatile memory cells containing the target memory cell.
2 more elements
A method of performing a read operation on a target memory cell of a non-volatile memory device having at least two strings of series-coupled non-volatile memory cells, the method comprising:
- precharging a selected bit line to a first potential, the selected bit line associated with the target memory cell;
- applying a second potential to a selected source line, the selected source line associated with the target memory cell;
- precharging one or more unselected source lines to a third potential, wherein the one or more unselected source lines are not associated with the target memory cell, wherein the third potential has a value different than the second potential and wherein the third potential is not a around potential of the memory device;
- and
- sensing a data value of the target memory cell from a voltage change in the selected bit line.
2 more elements
A method of performing a read operation on a target memory cell of a memory device having a plurality of blocks of non-volatile memory cells arranged as a plurality of series-coupled strings of memory cells, the method comprising:
- precharging a first bit line to a first potential, the first bit line associated with the target memory cell in a first block of non-volatile memory cells;
- applying a second potential to a first source line, the first source line associated with the first block of non-volatile memory cells;
- precharging one or more second source lines to a third potential, wherein the third potential has a value different than the second potential, wherein the third potential is not a ground potential of the memory device and wherein each of the second source lines is associated with a block of non-volatile memory cells other than the first block of non-volatile memory cells;
- and
- sensing a data value of the target memory cell from a voltage change in the first bit line.
2 more elements
A method of performing a read operation on a target memory cell of a memory device having a plurality of blocks of non-volatile memory cells arranged as a plurality of series-coupled strings of memory cells, the method comprising:
- applying a first potential to a first bit line, the first bit line associated with the target memory cell in a first block of non-volatile memory cells;
- applying a second potential to a first source line, the first source line associated with the first block of non-volatile memory cells;
- applying a third potential to one or more second source lines, wherein the third potential has a value different than the second potential, wherein the third potential is not a ground potential of the memory device and wherein each of the second source lines is associated with a block of non-volatile memory cells other than the first block of non-volatile memory cells;
- and
- reading a data value of the target memory cell from the series-coupled string of memory cells containing the target memory cell.
2 more elements
A memory device, comprising:
- an array of memory cells having strings of series-coupled non-volatile memory cells, each string of series-coupled non-volatile memory cells selectively coupled between a source line and a bit line;
- and
- circuitry for access of the array of memory cells, wherein the circuitry for access is adapted to perform a method of reading a target memory cell of the memory device, the method comprising:
- applying a first potential to a bit line selectively coupled to the target memory cell;
- applying a second potential to the source line selectively coupled to the target memory cell;
- applying a third potential to one or more source lines selectively coupled to the bit line and not selectively coupled to the target memory cell, wherein the third potential has a value different than the second potential and wherein the third potential is not a ground potential of the memory device;
- and
- reading a data value of the target memory cell from a string of non-volatile memory cells containing the target memory cell.
5 more elements
A memory device, comprising:
- an array of memory cells having strings of series-coupled non-volatile memory cells, each string of series-coupled non-volatile memory cells selectively coupled between a source line and a bit line;
- and
- circuitry for access of the array of memory cells, wherein the circuitry for access is adapted to perform a method of reading a target memory cell of the memory device, the method comprising:
- precharging a selected bit line to a first potential, the selected bit line associated with the target memory cell;
- applying a second potential to a selected source line, the selected source line associated with the target memory cell;
- precharging one or more unselected source lines to a third potential, wherein the one or more unselected source lines are not associated with the target memory cell, wherein the third potential has a value different than the second potential and wherein the third potential is not a ground potential of the memory device;
- and
- sensing a data value of the target memory cell from a voltage change in the selected bit line.
5 more elements
A memory device, comprising:
- an array of memory cells having strings of series-coupled non-volatile memory cells, each string of series-coupled non-volatile memory cells selectively coupled between a source line and a bit line;
- and
- circuitry for access of the array of memory cells, wherein the circuitry for access is adapted to perform a method of reading a target memory cell of the memory device, the method comprising:
- precharging a first bit line to a first potential, the first bit line associated with the target memory cell in a first block of non-volatile memory cells;
- applying a second potential to a first source line, the first source line associated with the first block of non-volatile memory cells;
- precharging one or more second source lines to a third potential, wherein the third potential has a value different than the second potential, wherein the third potential is not a ground potential of the memory device and wherein each of the second source lines is associated with a block of non-volatile memory cells other than the first block of non-volatile memory cells;
- and
- sensing a data value of the target memory cell from a voltage change in the first bit line.
5 more elements
A memory device, comprising:
- an array of memory cells having strings of series-coupled non-volatile memory cells, each string of series-coupled non-volatile memory cells selectively coupled between a source line and a bit line;
- and
- circuitry for access of the array of memory cells, wherein the circuitry for access is adapted to perform a method of reading a target memory cell of the memory device, the method comprising:
- applying a first potential to a first bit line, the first bit line associated with the target memory cell in a first block of non-volatile memory cells;
- applying a second potential to a first source line, the first source line associated with the first block of non-volatile memory cells;
- applying a third potential to one or more second source lines, wherein the third potential has a value different than the second potential, wherein the third potential is not a ground potential of the memory device and wherein each of the second source lines is associated with a block of non-volatile memory cells other than the first block of non-volatile memory cells;
- and
- reading a data value of the target memory cell from the series-coupled string of memory cells containing the target memory cell.
5 more elements
A memory module, comprising:
- a plurality of contacts;
- and
- two or more memory devices, each having access lines selectively coupled to the plurality of contacts;
- wherein at least one of the memory devices comprises:
- an array of memory cells having strings of series-coupled non-volatile memory cells, each string of series-coupled non-volatile memory cells selectively coupled between a source line and a bit line;
- and
- circuitry for access of the array of memory cells, wherein the circuitry for access is adapted to perform a method of reading a target memory cell of the memory device, the method comprising:
- applying a first potential to a bit line selectively coupled to the target memory cell;
- applying a second potential to the source line selectively coupled to the target memory cell;
- applying a third potential to one or more source lines selectively coupled to the bit line and not selectively coupled to the target memory cell, wherein the third potential has a value different than the second potential and wherein the third potential is not a ground potential of the memory device;
- and
- reading a data value of the target memory cell from a string of non-volatile memory cells containing the target memory cell.
9 more elements
A memory module, comprising:
- a plurality of contacts;
- and
- two or more memory devices, each having access lines selectively coupled to the plurality of contacts;
- wherein at least one of the memory devices comprises:
- an array of memory cells having strings of series-coupled non-volatile memory cells, each string of series-coupled non-volatile memory cells selectively coupled between a source line and a bit line;
- and
- circuitry for access of the array of memory cells, wherein the circuitry for access is adapted to perform a method of reading a target memory cell of the memory device, the method comprising:
- precharging a selected bit line to a first potential, the selected bit line associated with the target memory cell;
- applying a second potential to a selected source line, the selected source line associated with the target memory cell;
- precharging one or more unselected source lines to a third potential, wherein the one or more unselected source lines are not associated with the target memory cell, wherein the third potential has a value different than the second potential and wherein the third potential is not a ground potential of the memory device;
- and
- sensing a data value of the target memory cell from a voltage change in the selected bit line.
9 more elements
A memory module, comprising:
- a plurality of contacts;
- and
- two or more memory devices, each having access lines selectively coupled to the plurality of contacts;
- wherein at least one of the memory devices comprises:
- an array of memory cells having strings of series-coupled non-volatile memory cells, each string of series-coupled non-volatile memory cells selectively coupled between a source line and a bit line;
- and
- circuitry for access of the array of memory cells, wherein the circuitry for access is adapted to perform a method of reading a target memory cell of the memory device, the method comprising:
- precharging a first bit line to a first potential, the first bit line associated with the target memory cell in a first block of non-volatile memory cells;
- applying a second potential to a first source line, the first source line associated with the first block of non-volatile memory cells;
- precharging one or more second source lines to a third potential, wherein the third potential has a value different than the second potential wherein the third potential is not a ground potential of the memory device and wherein each of the second source lines is associated with a block of non-volatile memory cells other than the first block of non-volatile memory cells;
- and
- sensing a data value of the target memory cell from a voltage change in the first bit line.
9 more elements
A memory module, comprising:
- a plurality of contacts;
- and
- two or more memory devices, each having access lines selectively coupled to the plurality of contacts;
- wherein at least one of the memory devices comprises:
- an array of memory cells having strings of series-coupled non-volatile memory cells, each string of series-coupled non-volatile memory cells selectively coupled between a source line and a bit line;
- and
- circuitry for access of the array of memory cells, wherein the circuitry for access is adapted to perform a method of reading a target memory cell of the memory device, the method comprising:
- applying a first potential to a first bit line, the first bit line associated with the target memory cell in a first block of non-volatile memory cells;
- applying a second potential to a first source line, the first source line associated with the first block of non-volatile memory cells;
- applying a third potential to one or more second source lines, wherein the third potential has a value different than the second potential, wherein the third potential is not a ground potential of the memory device and wherein each of the second source lines is associated with a block of non-volatile memory cells other than the first block of non-volatile memory cells;
- and
- reading a data value of the target memory cell from the series-coupled string of memory cells containing the target memory cell.
9 more elements
A memory module, comprising:
- a housing having a plurality of contacts;
- and
- one or more memory devices enclosed in the housing and selectively coupled to the plurality of contacts;
- wherein at least one of the memory devices comprises:
- an array of memory cells having strings of series-coupled non-volatile memory cells, each string of series-coupled non-volatile memory cells selectively coupled between a source line and a bit line;
- and
- circuitry for access of the array of memory cells, wherein the circuitry for access is adapted to perform a method of reading a target memory cell of the memory device, the method comprising:
- applying a first potential to a bit line selectively coupled to the target memory cell;
- applying a second potential to the source line selectively coupled to the target memory cell;
- applying a third potential to one or more source lines selectively coupled to the bit line and not selectively coupled to the target memory cell, wherein the third potential has a value different than the second potential and wherein the third potential is not a ground potential of the memory device;
- and
- reading a data value of the target memory cell from a string of non-volatile memory cells containing the target memory cell.
9 more elements
A memory module, comprising:
- a housing having a plurality of contacts;
- and
- one or more memory devices enclosed in the housing and selectively coupled to the plurality of contacts;
- wherein at least one of the memory devices comprises:
- an array of memory cells having strings of series-coupled non-volatile memory cells, each string of series-coupled non-volatile memory cells selectively coupled between a source line and a bit line;
- and
- circuitry for access of the array of memory cells, wherein the circuitry for access is adapted to perform a method of reading a target memory cell of the memory device, the method comprising:
- precharging a selected bit line to a first potential, the selected bit line associated with the target memory cell;
- applying a second potential to a selected source line, the selected source line associated with the target memory cell;
- precharging one or more unselected source lines to a third potential, wherein the one or more unselected source lines are not associated with the target memory cell, wherein the third potential has a value different than the second potential and wherein the third potential is not a ground potential of the memory device;
- and
- sensing a data value of the target memory cell from a voltage change in the selected bit line.
9 more elements
A memory module, comprising:
- a housing having a plurality of contacts;
- and
- one or more memory devices enclosed in the housing and selectively coupled to the plurality of contacts;
- wherein at least one of the memory devices comprises:
- an array of memory cells having strings of series-coupled non-volatile memory cells, each string of series-coupled non-volatile memory cells selectively coupled between a source line and a bit line;
- and
- circuitry for access of the array of memory cells, wherein the circuitry for access is adapted to perform a method of reading a target memory cell of the memory device, the method comprising:
- precharging a first bit line to a first potential, the first bit line associated with the target memory cell in a first block of non-volatile memory cells;
- applying a second potential to a first source line, the first source line associated with the first block of non-volatile memory cells;
- precharging one or more second source lines to a third potential, wherein the third potential has a value different than the second potentials wherein the third potential is not a ground potential of the memory device and wherein each of the second source lines is associated with a block of non-volatile memory cells other than the first block of non-volatile memory cells;
- and
- sensing a data value of the target memory cell from a voltage change in the first bit line.
9 more elements
A memory module, comprising:
- a housing having a plurality of contacts;
- and
- one or more memory devices enclosed in the housing and selectively coupled to the plurality of contacts;
- wherein at least one of the memory devices comprises:
- an array of memory cells having strings of series-coupled non-volatile memory cells, each string of series-coupled non-volatile memory cells selectively coupled between a source line and a bit line;
- and
- circuitry for access of the array of memory cells, wherein the circuitry for access is adapted to perform a method of reading a target memory cell of the memory device, the method comprising:
- applying a first potential to a first bit line, the first bit line associated with the target memory cell in a first block of non-volatile memory cells;
- applying a second potential to a first source line, the first source line associated with the first block of non-volatile memory cells;
- applying a third potential to one or more second source lines, wherein the third potential has a value different than the second potential wherein the third potential is not a ground potential of the memory device and wherein each of the second source lines is associated with a block of non-volatile memory cells other than the first block of non-volatile memory cells;
- and
- reading a data value of the target memory cell from the series-coupled string of memory cells containing the target memory cell.
9 more elements
An electronic system, comprising:
- a processor;
- and
- one or more memory device coupled to the processor, wherein at least one of the memory devices comprises:
- an array of memory cells having strings of series-coupled non-volatile memory cells, each string of series-coupled non-volatile memory cells selectively coupled between a source line and a bit line;
- and
- circuitry for access of the array of memory cells, wherein the circuitry for access is adapted to perform a method of reading a target memory cell of the memory device, the method comprising:
- applying a first potential to a bit line selectively coupled to the target memory cell;
- applying a second potential to the source line selectively coupled to the target memory cell;
- applying a third potential to one or more source lines selectively coupled to the bit line and not selectively coupled to the target memory cell, wherein the third potential has a value different than the second potential and wherein the third potential is not a ground potential of the memory device;
- and
- reading a data value of the target memory cell from a string of non-volatile memory cells containing the target memory cell.
8 more elements
An electronic system, comprising:
- a processor;
- and
- one or more memory device coupled to the processor, wherein at least one of the memory devices comprises:
- an array of memory cells having strings of series-coupled non-volatile memory cells, each string of series-coupled non-volatile memory cells selectively coupled between a source line and a bit line;
- and
- circuitry for access of the array of memory cells, wherein the circuitry for access is adapted to perform a method of reading a target memory cell of the memory device, the method comprising:
- precharging a selected bit line to a first potential, the selected bit line associated with the target memory cell;
- applying a second potential to a selected source line, the selected source line associated with the target memory cell;
- precharging one or more unselected source lines to a third potential, wherein the one or more unselected source lines are not associated with the target memory cell, wherein the third potential has a value different than the second potential and wherein the third potential is not a ground potential of the memory device;
- and
- sensing a data value of the target memory cell from a voltage change in the selected bit line.
8 more elements
An electronic system, comprising:
- a processor;
- and
- one or more memory device coupled to the processor, wherein at least one of the memory devices comprises:
- an array of memory cells having strings of series-coupled non-volatile memory cells, each string of series-coupled non-volatile memory cells selectively coupled between a source line and a bit line;
- and
- circuitry for access of the array of memory cells, wherein the circuitry for access is adapted to perform a method of reading a target memory cell of the memory device, the method comprising:
- precharging a first bit line to a first potential, the first bit line associated with the target memory cell in a first block of non-volatile memory cells;
- applying a second potential to a first source line, the first source line associated with the first block of non-volatile memory cells;
- precharging one or more second source lines to a third potential, wherein the third potential has a value different than the second potential, wherein the third potential is not a ground potential of the memory device and wherein each of the second source lines is associated with a block of non-volatile memory cells other than the first block of non-volatile memory cells;
- and
- sensing a data value of the target memory cell from a voltage change in the first bit line.
8 more elements
An electronic system, comprising:
- a processor;
- and
- one or more memory device coupled to the processor, wherein at least one of the memory devices comprises:
- an array of memory cells having strings of series-coupled non-volatile memory cells, each string of series-coupled non-volatile memory cells selectively coupled between a source line and a bit line;
- and
- circuitry for access of the array of memory cells, wherein the circuitry for access is adapted to perform a method of reading a target memory cell of the memory device, the method comprising:
- applying a first potential to a first bit line, the first bit line associated with the target memory cell in a first block of non-volatile memory cells;
- applying a second potential to a first source line, the first source line associated with the first block of non-volatile memory cells;
- applying a third potential to one or more second source lines, wherein the third potential has a value different than the second potential, wherein the third potential is not a ground potential of the memory device and wherein each of the second source lines is associated with a block of non-volatile memory cells other than the first block of non-volatile memory cells;
- and
- reading a data value of the target memory cell from the series-coupled string of memory cells containing the target memory cell.
8 more elements
Dependencies are inferred from the claim text.