Bit-symbol recognition method and structure for multiple-bit storage in non-volatile memories

A method of determining the particular multi-bit value out of N possible values, where N is an integer equal to two or more, stored on a storage layer of a MOSFET in a non-volatile memory cell, said MOSFET also including a control gate, which comprises:

• applying in sequence a series of voltages to said control gate, said voltages changing incrementally as a function of time;
• monitoring the output signal on an output lead controlled by said MOSFET to determine when the MOSFET changes from one state to another state by detecting a change in said output signal in response to said MOSFET changing from one state to another state;
• and
• using the change in said output signal to identify the particular one of said N possible values which is stored on said storage layer;
• wherein said step of applying in sequence a series of voltages to said control gate comprises:
• generating a sequence of binary code words, each binary code word changing in value by a selected amount from the previous binary code word;
• applying each binary code word in said sequence to a digital-to-analog converter and also to a buffer, said digital-to-analog converter producing a unique output signal in response to each binary code word;
• applying each output signal from said digital-to-analog converter to the control gate of a MOSFET having a storage layer;
• detecting the particular code word which causes the MOSFET to transition from one state to another state;
• and
• providing, in response to the change in the operating state of the MOSFET, the value of said particular code word to said buffer for said buffer to provide to an output terminal or bus.

A non-volatile memory structure comprising:

• a MOSFET including a storage layer and a control gate;
• a digital-to-analog converter connected to provide at least two different voltages to said control gate;
• a source of at least two digital multi-bit words representing said at least two different voltages;
• an output buffer for receiving a selected one of said at least two digital multi-bit words;
• a load connected in series with said MOSFET to provide a node between said load and said MOS transistor;
• a comparator arranged to determine a change in signal at said node, said change representing a change in state of said MOSFET as a result of a voltage applied to said control gate matching the threshold voltage of said MOSFET;
• and
• a control circuit for detecting said change in output voltage from the comparator, said control circuit providing a signal to the output buffer thereby to allow the output buffer to receive one or more signals representing the value of the voltage from said converter applied to said control gate which causes said change in state of said MOSFET, said control voltage corresponding to the multi-bit data stored on the storage layer of said MOSFET.

A method for determining the particular multi-bit value stored in a non-volatile memory cell which comprises:

• storing a selected charge corresponding to a multi-bit word on the floating gate of an MOS transistor which comprises a source region, a drain region, a channel region between the source and drain region, a control gate separated by a dielectric from said underlying channel region, and a storage layer formed in said dielectric between said control gate and said channel region, said storage layer being adapted to hold any one of N different charges to represent any one of a corresponding number of multi-bit values, where N is a selected number;
• applying in sequence a series of voltages to said control gate, said voltages changing incrementally as a function of time;
• monitoring the output voltage from said MOS transistor to determine when the MOS transistor changes from one state to another state;
• producing an output signal at the time said MOSFET changes from one state to another state;
• and
• applying said output signal to a control circuit which causes to be provided on an output terminal or bus one or more signals representing the voltage applied to the control gate which changed the state of said MOS transistor, said voltage corresponding to the charge stored on said storage layer;
• wherein said step of applying in sequence a series of voltages to said control gate comprises:
• generating a sequence of binary code words, each binary code word changing in value by a selected amount from the previous binary code word;
• applying said binary code words to a digital-to-analog converter and also to a buffer;
• detecting the particular code word which causes the MOS transistor to transition from one state to another state;
• and
• providing, in response to the change in the operating state of the MOS transistor, the value of said particular code word to the buffer for transmission to an output terminal.