Memory with a core-based virtual ground and dynamic reference sensing scheme
AssigneeSpansion LLC
InventorsMing-Huei Shieh, Kazuhiro Kurihara
Life of this patent
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Abstract
A core-based multi-bit memory (400) having a dual-bit dynamic referencing architecture (408, 410) fabricated on the memory core (401). A first reference array (408) and a second reference array (410) are fabricated on the memory core (401) such that a reference cell pair (185) comprising one cell (182) of the first reference array (408) and a corresponding cell (184) of the second reference array (410) are read and averaged to provide a reference voltage for reading a data array(s).
Claims13
A method associated with a multi-bit memory cell having a redundancy array located proximate or adjacent to groups of data sectors, comprising,
- pre-charging first and second reference arrays each comprised of a plurality of reference cells wherein a program order for precharging the reference cells in the first and second reference arrays is from a last reference cell in the first reference array and a first reference cell in the second reference array to a first reference cell in the first reference array and a last reference cell in the second reference array to reduce transmitting effect prior to averaging voltage levels associated therewith;
- and
- averaging a first bit value of a first reference cell of the first reference array with a second bit value of a second reference cell of the second reference array to generate a reference voltage for use with a data cell read operation.
Dependencies are inferred from the claim text.