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US 7,606,062 B2Granted
Ultra low voltage and minimum operating voltage tolerant register file
AssigneeIntel Corporation
InventorsSteven K. Hsu, Amit Agarwal, Ram K. Krishnamurthy
Life of this patent
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Abstract
Methods and apparatus relating ultra-low voltage memory bit cells are described. In an embodiment, an ultra-low voltage memory device is provided using redundant paths to data storage nodes controlled by complementary write word lines. Other embodiments are also described.
Claims15
A processor comprising:
- a register file to store one or more bits of data, the register file to comprise a plurality of memory bit cells;
- and
- at least one of the plurality of memory bit cells to comprise:
- a first data storage element having a first transistor and a second transistor;
- a third transistor coupled between a write bit line and a bit node of the first data storage element;
- and
- a fourth transistor coupled between the write bit line and the bit node of the first data storage element,
- wherein the first and third transistors are to write a first value to the bit node and the second and fourth transistors are to write a second value to the bit node, wherein the first value and second value are complementary.
5 more elements
An apparatus comprising:
- a first transistor coupled to a write bit line, a write word line, and a bit node;
- a second transistor coupled to a complementary write bit line, the write word line, and a complementary bit node;
- a third transistor coupled to the write bit line, a complementary write word line, and the bit node, wherein the third transistor is coupled to the write bit line and the bit node in parallel with the first transistor;
- and
- a fourth transistor coupled to the complementary write bit line, the complementary write word line, and the complementary bit node, wherein the fourth transistor is coupled to the complementary write bit line and the complementary bit node in parallel with the second transistor.
2 more elements
Dependencies are inferred from the claim text.