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US 7,606,061 B2Granted
SRAM device with a power saving module controlled by word line signals
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsSubramani Kengeri, Jhon-Jhy Liaw
Life of this patent
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Abstract
An SRAM device include: a latch unit for retaining data; one or more pass gate transistors controlled by a word line for coupling the latch unit to a bit line and a complementary bit line; and a power saving module coupled to the latch unit for raising a source voltage of the latch unit in response to a control signal on the word line, thereby reducing a leakage current for the latch unit.
Claims16
A static random access memory (SRAM) device comprising:
- a latch unit for retaining data;
- one or more pass gate transistors controlled by a word line for coupling the latch unit to a bit line and a complementary bit line, wherein the latch unit further comprises:
- a first PMOS transistor having a source coupled to a supply voltage;
- a first NMOS transistor having a drain and a gate coupled to a drain and a gate of the first PMOS transistor, respectively;
- a second PMOS transistor having a source coupled to the supply voltage;
- and
- a second NMOS transistor having a drain and a gate coupled to a drain and a gate of the second PMOS transistor, respectively;
- and
- a power saving module coupled to the latch unit for raising a source voltage of the latch unit in response to a control signal on the word line, thereby reducing a leakage current for the latch unit, wherein the power saving module comprises a first source line coupled to a source of the first NMOS transistor, and a second source line coupled to a source of the second NMOS transistor.
6 more elements
A static random access memory (SRAM) device having a plurality of SRAM cells, each of which comprises:
- a first PMOS transistor having a source coupled to a supply voltage;
- a first NMOS transistor having a drain and a gate coupled to a drain and a gate of the first PMOS transistor, respectively;
- a second PMOS transistor having a source coupled to the supply voltage;
- a second NMOS transistor having a drain and a gate coupled to a drain and a gate of the second PMOS transistor, respectively, the gates of the first NMOS and PMOS transistors being coupled to the drains of the second NMOS and PMOS transistors to form a data storage node, and the gates of the second NMOS and PMOS transistors being coupled to the drains of the first NMOS and PMOS transistors to form a complementary data storage node;
- a first pass gate transistor controlled by a word line for selectively coupling the data storage node to a bit line;
- a second pass gate transistor controlled by the word line for selectively coupling the complementary data storage node to a complementary bit line;
- and
- a power saving module coupled to sources of the first and second NMOS transistors for raising their source voltages when a control signal on the word line is low, thereby reducing a leakage current from the power supply to the sources of the first and second NMOS transistors, and
- wherein the power saving module comprises a first source line coupled to the source of the first NMOS transistor, and a second source line coupled to the source of the second NMOS transistor.
6 more elements
Dependencies are inferred from the claim text.