Metal line layout in a memory cell
AssigneeArm Limited
InventorsKarl Lin Wang, Hemangi Umakant Gajjewar
Life of this patent
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Abstract
A memory cell includes polysilicon gates 2 running in a first direction. A sequence of layers metal lines includes a layer of bit lines 4 running in a second direction substantially orthogonal to the first direction followed by data lines 6 running in that second direction and then word lines 8 running in the first direction. The data lines 6 are precharged to a value which is held whilst the bit lines 4 are being used to sense data values stored within a memory cell.
Claims19
A memory cell comprising:
- polysilicon gates disposed substantially parallel to a first direction and forming part of at least one gate within said memory cell;
- and
- a sequence of spaced layers of metal lines comprising:
- (i) a bit line disposed substantially parallel to a second direction, said second direction being substantially orthogonal to said first direction;
- (ii) a data line disposed substantially parallel to said second direction and in one of (a) a same layer as said bit line;
- and (b) a layer above said bit line;
- and
- (iii) a word line disposed substantially parallel to said first direction and above said data line.
An integrated circuit comprising a plurality of memory cells each comprising:
- polysilicon gates disposed substantially parallel to a first direction and forming part of at least one gate within said memory cell;
- and
- a sequence of spaced layers of metal lines comprising:
- (i) a bit line disposed substantially parallel to a second direction, said second direction being substantially orthogonal to said first direction;
- (ii) a data line disposed substantially parallel to said second direction and in one of (a) a same layer as said bit line;
- and (b) a layer above said bit line;
- and
- (iii) a word line disposed substantially parallel to said first direction and above said data line.
A method of forming a memory cell having polysilicon gates disposed substantially parallel to a first direction and forming part of at least one gate within said memory cell and a sequence of spaced layers of metal lines, said method comprising the steps of:
- (i) forming a bit line disposed substantially parallel to a second direction, said second direction being substantially orthogonal to said first direction;
- (ii) forming a data line disposed substantially parallel to said second direction and in one of (a) a same layer as said bit line;
- and (b) a layer above said bit line;
- and
- (iii) forming a word line disposed substantially parallel to said first direction and above said data line.
Dependencies are inferred from the claim text.