Process for manufacturing a phase change memory array in Cu-damascene technology and phase change memory array thereby manufactured

A process for manufacturing a phase change memory array, comprising the steps of:

• forming a plurality of phase change memory cells in an array region of a semiconductor wafer, said phase change memory cells being arranged in rows and columns according to a row direction and to a column direction, respectively;
• forming electrical components in a control region of said semiconductor wafer;
• forming a plurality of conductive first bit line portions for mutually connecting phase change memory cells arranged on a same column;
• and
• forming a plurality of conductive second bit line portions for connecting respective said first bit line portions to respective said electrical components, wherein said second bit line portions lie on and in direct contact with the respective first bit line portions and project from the respective first bit line portions in said column direction to the respective electrical components.

A phase change memory device comprising

• a plurality of phase change memory cells arranged in an array region of a semiconductor wafer, said phase change memory cells being arranged in rows and columns according to a row direction and to a column direction, respectively;
• a control circuit arranged in a control region of said semiconductor wafer;
• a plurality of conductive first bit line portions for mutually connecting phase change memory cells arranged in a same column;
• conductive first level electrical interconnection structures;
• and
• conductive second level electrical interconnection structures arranged above said first level electrical interconnection structures, wherein said first level electrical interconnection structures include conductive second bit line portions laying on and in direct contact with said first bit line portions and projecting from said first bit line portions in said column direction for connecting said first bit line portions to said control circuit.

A phase change memory device comprising:

• a plurality of phase change memory cells in an array region of a semiconductor wafer, said phase change memory cells being arranged in rows and columns according to a row direction and to a column direction, respectively;
• a plurality of electrical components in a control region of said semiconductor wafer;
• a plurality of conductive first bit line portions, each mutually connecting the phase change memory cells arranged in a respective one of the columns;
• and
• a plurality of conductive second bit line portions for connecting respective said first bit line portions to respective said electrical components, wherein said second bit line portions overlie and are in direct contact with the respective first bit line portions and project from the respective first bit line portions in said same column to the respective electrical components.