Cache hit logic of cache memory and processor chip having the same
AssigneeSamsung Electronics Co., Ltd.
InventorKwang-Il Kim
Life of this patent
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Abstract
A processor chip having a cache hit logic for determining whether data required by a processor is stored in a cache memory includes a dummy cell string that operates the same as a sense amplifier for sensing a tag address stored in a tag memory cell array and a comparison logic for determining whether the sensed tag address coincides with an input tag address, a dummy sense amplifier, and a dummy comparison logic. The processor chip having the cache hit logic improves the reliability of a hit signal and operation speed is not limited.
Claims23
A data processing system comprising:
- a processor;
- and
- a cache memory configured to store data to be used at the processor and having a cache hit logic for determining whether data requested by the processor is stored in the cache memory, wherein
- the cache hit logic includes:
- a tag memory cell array having tag memory cells arranged in rows and columns to store tag addresses;
- a row decoder for selecting the rows;
- a column decoder for selecting the columns;
- a sense amplifier for sensing a tag address stored in a cell of the tag memory cell array selected by the row decoder and the column decoder in response to an activation of an enable signal;
- and
- a comparison circuit for comparing the sensed tag address with an input tag address when a time required for the sense amplifier to sense the tag address has passed after the enable signal is activated, to output a hit signal corresponding to the comparison result, wherein the comparison circuit activates an output enable signal when a time required for the sense amplifier to sense the tag address has passed after the enable signal is activated.
A data processing system comprising:
- a processor;
- and
- a cache memory configured to store data to be used at the processor and having a cache hit logic for determining whether data requested by the processor is stored in the cache memory, wherein
- the cache hit logic includes:
- a tag memory cell array having tag memory cells arranged in rows and columns to store tag addresses;
- a row decoder for selecting the rows;
- a column decoder for selecting the columns;
- a sense amplifier for sensing a tag address stored in a cell of the tag memory cell array selected by the row decoder and the column decoder in response to an activation of an enable signal;
- a comparison circuit for comparing the sensed tag address with an input tag address;
- a dummy cell string having dummy cells arranged in a column direction of the tag memory cell array;
- a dummy sense amplifier for sensing a dummy address stored in a dummy cell selected by the row decoder in response to the activation of the enable signal;
- and
- an output circuit for outputting the comparison signal from the comparison logic as a hit signal when the dummy sense amplifier senses the dummy address.
A data processing system comprising:
- a processor;
- and
- a cache memory configured to store data to be used at the processor and having a cache hit logic for determining whether data requested by the processor is stored in the cache memory, wherein
- the cache hit logic includes:
- a tag memory cell array having tag memory cells arranged in rows and columns to store tag addresses;
- a row decoder for selecting the rows;
- a column decoder for selecting the columns;
- a sense amplifier for sensing a tag address stored in a cell of the tag memory cell array selected by the row decoder and the column decoder in response to an activation of an enable signal;
- a comparison circuit for comparing the sensed tag address with an input tag address;
- a dummy sense amplifier for receiving a source voltage and a ground voltage to output a pair of complementary dummy address bits in response to the activation of the enable signal;
- and
- an output circuit for outputting the comparison signal from the comparison logic as a hit signal when the dummy sense amplifier outputs the pair of complementary dummy address bits.
A cache hit detection method in a cache memory having a tag memory cell array which stores a tag address and is composed of tag memory cells arranged in rows and columns, the method comprising:
- (a) sensing the tag address of the tag memory cell corresponding to a selected row and column in response to an enable signal;
- (b) comparing the sensed tag address with an input tag address;
- (c) activating an output enable signal when a time required for the sense amplifier to sense the tag address of the tag memory cell has passed;
- and
- (d) outputting a hit signal corresponding to the comparison result in response to the output enable signal.
A cache hit detection method in a cache memory having a tag memory cell array which stores a tag address and is composed of tag memory cells arranged in rows and columns, the method comprising:
- (a) sensing the tag address of the tag memory cell corresponding to a selected row and column in response to an enable signal;
- (b) sensing the dummy address of the dummy cell corresponding to the selected row in response to the enable signal;
- (c) comparing the sensed tag address with an input tag address;
- (d) activating an output enable signal in response to the sensed dummy address when a time required for the sense amplifier to sense the tag address of the tag memory cell has passed;
- and
- (e) outputting a hit signal corresponding to the comparison result in response to the output enable signal.
A cache hit detection method in a cache memory having a tag memory cell array which stores a tag address and is composed of tag memory cells arranged in rows and columns, the method comprising:
- (a) sensing the tag address of the tag memory cell corresponding to a selected row and column in response to an enable signal;
- (b) sensing the dummy address of the dummy cell in response to the enable signal;
- (c) comparing the sensed tag address with an input tag address;
- (d) activating an output enable signal in response to the sensed dummy address when a time required for the sense amplifier to sense the tag address of the tag memory cell has passed;
- and
- (e) outputting a hit signal corresponding to the comparison result in response to the output enable signal.
Dependencies are inferred from the claim text.