Power semiconductor device architecture for output transistor protection

A system comprising:

• a power semiconductor device
• a battery feeding a power supply voltage to said power semiconductor device;
• and
• a load receiving an output current from said power semiconductor device,
• wherein a power semiconductor device includes:
• an output transistor connected between a power supply terminal receiving said power supply voltage and an output terminal connected with said load;
• a load control circuit adapted to feed said gate voltage to said gate of said output transistor, and to stop feeding said gate voltage to said output transistor when short-circuiting of said load occurs;
• and
• a pull-up circuit connected between said power supply terminal and said gate of said output transistor, and adapted to discharge electric charges on said gate of said output transistor, when short-circuiting of said load occurs with a voltage level on said power supply terminal lowered below said power supply voltage.

A system comprising:

• a power semiconductor device
• a battery feeding a power supply voltage to said power semiconductor device;
• a load receiving an output current from said power semiconductor device;
• and
• a chassis connected to a negative electrode of said battery,
• wherein said power semiconductor device includes:
• an output transistor connected between a power supply terminal receiving said power supply voltage and an output terminal connected to said load;
• a load control circuit connected to a gate of said output transistor;
• and
• a pull-up circuit connected between said power supply terminal and said gate of said output transistor, including:
• a pull-up transistor connected to said power supply terminal and said gate of said output transistor;
• and
• a diode connected between said pull-up transistor and said gate of said output transistor,
• wherein said pull-up transistor is an N-channel depletion type MOSFET having a source and backgate connected to said power supply terminal and a gate earth-grounded, and
• wherein said diode has a cathode connected to a drain of said pull-up transistor and an anode connected to said gate of said output transistor.