Demultiplexer and display device using the same

A display device including a plurality of data lines comprising a first data line and a second data line, a plurality of scan lines for transmitting select signals, and a plurality of pixel circuits coupled to the data lines and the scan lines, the display device comprising:

• a data driver for supplying data currents corresponding to image signals to be displayed during a plurality of frames comprising a first frame and a second frame;
• a demultiplexer having an input terminal coupled to the data driver, the demultiplexer for demultiplexing the data currents to output as demultiplexed data currents;
• a switch unit for switching between output terminals of the demultiplexer comprising a first output terminal and a second output terminal and the data lines, wherein the switching unit is configured to electrically couple concurrently the first output terminal to the first data line and the second output terminal to the second data line in the first frame and to electrically couple concurrently the first output terminal to the second data line and the second output terminal to the first data line during the second frame;
• and
• a scan driver for supplying the select signals to the scan lines.

A display device including a plurality of data lines comprising first and second data lines, a plurality of scan lines for transmitting select signals, and a plurality of pixel circuits coupled to the data lines and the scan lines, the display device comprising:

• a data driver for supplying data currents corresponding to image signals;
• a demultiplexer including first and second sample/hold circuit groups each having an input terminal coupled to the data driver, and configured for demultiplexing the data currents to output as demultiplexed data currents;
• a switch unit for switching between output terminals of the first and second sample/hold circuit groups and the data lines;
• and
• a scan driver for supplying the select signals to the scan lines,
• wherein the first sample/hold circuit group includes first and third sample/hold circuits each having an input terminal and an output terminal, wherein the input terminals of the first and third sample/hold circuits are coupled with each other, and the output terminals of the first and third sample/hold circuits are coupled with each other,
• wherein the second sample/hold circuit group includes second and fourth sample/hold circuits, each having an input terminal and an output terminal, wherein the input terminals of the second and fourth sample/hold circuits are coupled with each other, and the output terminals of the second and fourth sample/hold circuits are coupled with each other, and
• wherein the first and second sample/hold circuit groups are configured such that the first sample/hold circuit supplies a corresponding one of the demultiplexed data currents to the first data line while the second sample/hold circuit supplies a corresponding one of the demultiplexed data currents to the second data line during a first frame, and the third sample/hold circuit supplies a corresponding one of the demultiplexed data currents to the second data line while the fourth sample/hold circuit supplies a corresponding one of the demultiplexed data currents to the first data line during a second frame.

A demultiplexer for programming a time-divided data current, which is input by a data driver, to a first signal line and a second signal line, comprising:

• first and second sample/hold circuit groups each having an input terminal coupled to a data driver, and configured for demultiplexing the data current to output as demultiplexed data currents;
• and
• a switch unit for switching between output terminals of the first and second sample/hold circuit groups and the first and second signal lines,
• wherein the first sample/hold circuit group includes first and third sample/hold circuits each having an input terminal and an output terminal, wherein the input terminals of the first and third sample/hold circuits are coupled with each other, and the output terminals of the first and third sample/hold circuits are coupled with each other,
• wherein the second sample/hold circuit group includes second and fourth sample/hold circuits each having an input terminal and an output terminal, wherein the input terminals of the second and fourth sample/hold circuits are coupled with each other, and the output terminals of the second and fourth sample/hold circuits are coupled with each other, and
• wherein the first and second sample/hold circuit groups are configured such that the first sample/hold circuit supplies a corresponding one of the demultiplexed data currents to the first signal line while the second sample/hold circuit supplies a corresponding one of the demultiplexed data currents to the second signal line during a first time period, and the third sample/hold circuit supplies a corresponding one of the demultiplexed data currents to the second signal line while the fourth sample/hold circuit supplies a corresponding one of the demultiplexed data currents to the first signal line during a second time period.

A demultiplexing method for outputting a time-divided and sequentially input data current to a first signal line and a second signal line, comprising:

• allowing first and second sample/hold circuits to sequentially sample the data current to store as first sampled data in a predetermined order during a first period;
• allowing the first and second sample/hold circuits to hold a current corresponding to the first sampled data to the signal lines during a second period;
• allowing third and fourth sample/hold circuits to sample the data current to store as second sampled data during the second period;
• and
• allowing the third and fourth sample/hold circuits to hold a current corresponding to the second sampled data to the signal lines during a third period,
• wherein the sample/hold circuits are configured such that one of first and second sample/hold circuits supplies the first sampled data to the first signal line while one of third and fourth sample/hold circuits supplies the second sampled data to the second signal line, and the other one of the first and second sample/hold circuits supplies the first sampled data to the second signal line while the other one of the third and fourth sample/hold circuits supplies the second sampled data to the first signal line.