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US 7,605,739 B2Granted
Differential flash ADC with dual resistance ladder legs receiving amplified inputs
AssigneeMarvell World Trade Ltd.
InventorSehat Sutardja
Life of this patent
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Abstract
A differential analog to digital converter (ADC) comprises a first resistance ladder leg including two resistances having first ends that communicate with a middle node. A second resistance ladder leg includes two resistances having first ends that communicate with a middle node. A first amplifier applies a voltage based upon a first phase of an input signal to said middle node of said first resistance ladder leg. A second amplifier applies a voltage based upon a second phase of the input signal to said middle node of said second resistance ladder leg.
Claims48
A differential analog to digital converter (ADC) comprising:
- a first resistance ladder leg including two resistances having first ends that communicate with a middle node;
- a second resistance ladder leg including two resistances having first ends that communicate with a middle node;
- a plurality of comparators, each having first and second inputs, wherein said first input communicates with one of said two resistances of said first resistance ladder leg, and said second input communicates with one of said two resistances of said second resistance ladder leg, wherein said first and second inputs of said plurality of comparators experience a propagation delay based upon an electrical distance of said first and second inputs from a corresponding one of said middle nodes;
- delay elements that communicate with said first and second inputs of said plurality of comparators and that adjust aggregate delays from corresponding ones of said middle nodes to said first and second inputs of said plurality of comparators;
- a first amplifier that applies a voltage based upon a first phase of an input signal to said middle node of said first resistance ladder leg;
- and
- a second amplifier that applies a voltage based upon a second phase of the input signal to said middle node of said second resistance ladder leg.
4 more elements
A method for converting from analog to digital comprising:
- providing a first resistance ladder leg including two resistances having first ends that communicate with a middle node;
- providing a second resistance ladder leg including two resistances having first ends that communicate with a middle node;
- providing a plurality of comparators, each having first and second inputs, wherein said first input communicates with one of said two resistances of said first resistance ladder leg, and said second input communicates with one of said two resistances of said second resistance ladder leg;
- latching an output from a corresponding one of said plurality of comparators at a delayed time based upon a propagation delay at least one of first and second inputs of said corresponding one of said plurality of comparators;
- applying a voltage based upon a first phase of an input signal to said middle node of said first resistance ladder leg;
- and
- applying a voltage based upon a second phase of the input signal to said middle node of said second resistance leg.
4 more elements
A differential analog to digital converter (ADC) comprising:
- a first resistance ladder leg including two resistances that communicate with a middle node;
- a second resistance ladder leg including two resistances having that communicate with a middle node;
- a first amplifier that applies a voltage based upon a first phase of an input signal to said middle node of said first resistance ladder leg;
- a second amplifier that applies a voltage based upon a second phase of the input signal to said middle node of said second resistance ladder leg;
- a plurality of comparators, each having first and second inputs, wherein said first inputs communicate with said first resistance ladder leg and said second inputs communicate with said second resistance ladder leg;
- and
- a plurality of delay elements associated with selected ones of said plurality of comparators.
4 more elements
A method comprising:
- providing a first resistance ladder leg including two resistances having first ends that communicate with a middle node;
- providing a second resistance ladder leg including two resistances having first ends that communicate with a middle node;
- applying a voltage based upon a first phase of an input signal to said middle node of said first resistance ladder leg;
- applying a voltage based upon a second phase of the input signal to said middle node of said second resistance ladder leg;
- providing a plurality of comparators, each having first and second inputs, wherein said first inputs communicate with said first resistance ladder leg and said second inputs communicate with said second resistance ladder leg;
- and
- providing a plurality of delay elements associated with selected ones of said plurality of comparators.
4 more elements
Dependencies are inferred from the claim text.