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US 7,605,726 B2Granted
Circuit and method for data alignment
AssigneeHynix Semiconductor Inc.
InventorSang-Yeon Byeon
Life of this patent
Estimating the term…
Abstract
A circuit for data alignment includes a first latch unit and a second latch unit. The first latch unit latches serial input data by using a plurality of first clocks with different phases and the same frequency to output latched data. The second latch unit latches the data from the first latch unit by using a plurality of second clocks with a lower frequency than the first clocks and more diverse phases to thereby output parallel data.
Claims17
A circuit for data alignment, comprising:
- a first latch unit for latching serial input data by using a plurality of first clocks with different phases and a same frequency to output latched data;
- and
- a second latch unit for latching the data from the first latch unit by using a plurality of second clocks with a lower frequency and more diverse phases than the first clocks to thereby output parallel data.
A circuit for data alignment, comprising:
- a first latch unit for latching serial input data by using clock and inverted clocks from outside to output latched data;
- and
- a second latch unit for latching the data from the first latch unit by using four second clocks with half frequency of the clocks and different phases to thereby output parallel data.
A method for data alignment, comprising:
- latching serial input data in a first latch unit using a plurality of first clocks with different phases and a same frequency;
- and
- latching the data latched in the first latch unit by using a plurality of second clocks with a lower frequency and more diverse phases than the first clocks to thereby output parallel data.
Dependencies are inferred from the claim text.