Power gating structure, semiconductor including the same and method of controlling a power gating

A power gating structure configured to control electrical connection between a power supply terminal and a virtual power supply node so as to operate a logic circuit in a plurality of operation modes, the structure comprising:

• a first path configured to control electrical connection between the power supply terminal and the virtual power supply node in response to a first control signal;
• and
• a second path configured to control electrical connection between the power supply terminal and the virtual power supply node in response to the first control signal and a second control signal, wherein the second path comprises a plurality of transistors that are serially coupled together between the power supply terminal and the virtual power supply node and configured to receive the first control signal and the second control signal,
• wherein the power supply terminal corresponds to a lower power supply voltage level, the power gating structure further comprising:
• a third path configured to control electrical connection between a higher power supply terminal having a higher power supply voltage level and a virtual higher power supply node in response to a third control signal;
• and
• a fourth path configured to control electrical connection between the higher power supply terminal and the virtual higher power supply node in response to the third control signal and a fourth control signal.

A power gating structure that controls electrical connection between a power supply terminal and a virtual power supply node so as to operate a logic circuit in a plurality of operation modes, wherein the power supply terminal corresponds to a higher power supply voltage level, the structure comprising:

• a first switch coupled between the power supply terminal and the virtual power supply node, and configured to operate in response to a first control signal;
• a second switch coupled to the virtual power supply node and configured to operate in conjunction with the first switch in response to the first control signal;
• and
• a third switch coupled between the second switch and the power supply terminal, and configured to be operated in response to a second control signal,
• wherein the first switch and the third switch comprise PMOS transistors, each PMOS transistor having a source connected to the power supply terminal, and the second switch comprises an NMOS transistor having a source connected to the virtual power supply node, and
• wherein the first control signal is configured to be at a logic “low” when the logic circuit is in an active mode, the first control signal is configured to be at a logic “high” and the second control signal at a logic “low” when the logic circuit is in a data retention mode, and both the first control signal and the second control signal are configured to be at a logic “high” when the logic circuit is in a power-down mode.

A semiconductor device comprising:

• a plurality of logic circuits coupled between first and second virtual power supply nodes and configured to operate in a plurality of operation modes;
• a plurality of first power gating circuits configured to control electrical connection between a first power supply terminal and the first virtual power supply node, each first power gating circuit including:
• a first path configured to control electrical connection between the first power supply terminal and the first virtual power supply node in response to a first inverted control signal that is inverted from a first control signal, and
• a second path configured to control electrical connection between the first power supply terminal and the first virtual power supply node in response to the first inverted control signal and a second inverted control signal that is inverted from a second control signal, wherein the second path comprises a plurality of transistors that are serially coupled together between the power supply terminal and the virtual power supply node and configured to receive the first inverted control signal and the second inverted control signal;
• and
• a plurality of second power gating circuits configured to control electrical connection between a second power supply terminal and the second virtual power supply node, each second power gating circuit including:
• a third path configured to control electrical connection between the second power supply terminal and the second virtual power supply node in response to the first control signal, and
• a fourth path configured to control electrical connection between the second power supply terminal and the second virtual power supply node in response to the first control signal and the second control signal.