System for glitch-free delay updates of a standard cell-based programmable delay
AssigneeLSI Corporation
InventorsTerence J. Magee, Thomas Hughes, Hui-Yin Seto
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Abstract
A method for glitch-free updates of a standard cell-based programmable delay including the steps of (A) generating an output signal in response to an input signal and a plurality of first control signals and (B) generating the plurality of first control signals in response to the output signal and a plurality of second control signals. The output signal may include a delayed version of the input signal. An amount of delay between the input signal and the output signal may be determined based upon the plurality of first control signals.
Claims20
A method for glitch-free updates of a standard cell-based programmable delay comprising the steps of:
- generating an output signal in response to an input signal and a plurality of first control signals, wherein said output signal comprises a delayed version of said input signal and an amount of delay between said input signal and said output signal is determined based upon said plurality of first control signals;
- and
- generating said plurality of first control signals in response to said output signal and a plurality of second control signals, wherein a first number of said plurality of second control signals and a second number of said plurality of second control signals are latched on opposite transitions of said output signal.
A delay cell comprising:
- means for generating an output signal in response to an input signal and a plurality of first control signals, wherein said output signal comprises a delayed version of said input signal and an amount of delay between said input signal and said output signal is determined based upon said plurality of first control signals;
- and
- means for generating said plurality of first control signals in response to said output signal and a plurality of second control signals, wherein a first number of said plurality of second control signals and a second number of said plurality of second control signals are latched on opposite transitions of said output signal.
An apparatus comprising:
- a first circuit configured to generate an output signal in response to an input signal and a plurality of first control signals, wherein said output signal comprises a delayed version of said input signal and an amount of delay between said input signal and said output signal is determined based upon said plurality of first control signals;
- and
- a second circuit configured to generate said plurality of first control signals in response to said output signal and a plurality of second control signals, wherein a first number of said plurality of second control signals and a second number of said plurality of second control signals are latched on opposite transitions of said output signal.
Dependencies are inferred from the claim text.