Clock generator and clock duty cycle correction method
AssigneeHynix Semiconductor Inc.
InventorHwang Hur
Life of this patent
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Abstract
A clock duty cycle correction (DCC) circuit for correcting a clock duty cycle of an external clock includes a phase comparator for comparing a phase of a rising clock with that of a falling clock to thereby output comparing signal; a DCC controller for outputting a DCC enable signal and a weight selection signal in response to the comparing signal and a first and a second lock state signal; a DCC mixing block for blending the rising clock and the falling clock in response to the DCC enable signal and the weight selection signal to thereby generate a rising and a falling pre-clock signals; and a clock selector for selectively output the rising and the falling pre-clock signals in response to the weight selection signal.
Claims11
An apparatus for correcting clock duty cycle, comprising:
- a first duty cycle correction (DCC) mixing block configured to mix a rising clock with a falling clock in response to a DCC enable signal and a weight selection signal to thereby generate a rising pre-clock signal;
- a second DCC mixing block configured to mix a falling clock with a rising clock in response to the DCC enable signal and the weight selection signal to thereby generate a falling pre-clock signal;
- and
- a clock selector for selectively outputting the rising and the falling pre-clock signals in response to the DCC enable signal and the weight selection signal,
- wherein the clock selector outputs the rising pre-clock signal as a rising feedback clock and the falling pre-clock signal as a falling feedback clock when the DCC enable signal is inactivated.
A method for correcting clock duty cycle, comprising:
- comparing a phase of a rising clock with a phase of a falling clock to thereby output a comparing signal;
- outputting a clock duty cycle correction (DCC) enable signal and a weight selection signal in response to the comparing signal and first and second lock state signals;
- mixing the rising clock with the falling clock in response to the DCC enable signal and the weight selection signal to thereby generate rising and falling pre-clock signals;
- and
- selectively outputting the rising and the falling pre-clock signals in response to the weight selection signal and the DCC enable signal,
- wherein the selectively outputting the rising and falling pre-clock signals includes outputting the rising pre-clock signal as a rising feedback clock and outputting the falling pre-clock signal as a falling feedback clock until the DCC enable signal is activated.
A clock duty cycle correction (DCC) circuit for correcting clock duty cycle, comprising:
- a phase comparator for comparing a phase of a rising clock with a phase of a falling clock to output a comparing signal;
- a DCC controller for outputting a DCC enable signal and a weight selection signal in response to the comparing signal and first and second lock state signals;
- a DCC mixing block for blending the rising clock and the falling clock in response to the DCC enable signal and the weight selection signal to thereby generate rising and falling pre-clock signals;
- and
- a clock selector for selectively outputting the rising and the falling pre-clock signals in response to the weight selection signal and the DCC enable signal;
- wherein the selectively outputting the rising and falling pre-clock signals includes outputting the rising pre-clock signal as a rising feedback clock and outputting the falling pre-clock signal as a falling feedback clock until the DCC enable signal is activated.
Dependencies are inferred from the claim text.