Device, system and method of delay calibration
AssigneeIntel Corporation
InventorsStefano Pellerano, Georgios Palaskas
Life of this patent
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Abstract
System and method of calibrating delay mismatch for high-spectral purity applications. For example, a method includes measuring the delay of one delay element at a time in a fixed topology by moving a time reference generated by an auxiliary delay-locked loop. The auxiliary DLL may have a replica structure of the primary DLL being calibrated. The calibration method uses one output clock signal of the primary DLL and measures delay mismatch using a reference phase previously measured using the same topology. The calibration method takes into account all delay mismatches in the topology up to the primary DLL output clock signal, including any delay generated by an associated multiplexer.
Claims13
A method of calibrating delay mismatch, the method comprising:
- aligning an output signal of a primary delay-locked loop having a plurality of delay elements with an auxiliary delay-locked loop having a replica structure of said primary delay-locked loop, to provide a reference time signal;
- measuring a delay of one of said delay elements based on a time difference between said reference time signal and an output time signal of said delay element being measured;
- and
- realigning the reference time signal in the auxiliary delay-locked loop for measuring a delay of a different one of said delay elements in the primary delay-locked loop.
An apparatus for calibrating delay mismatch, the apparatus comprising:
- a primary delay-locked loop having a plurality of delay elements to be calibrated for relative delay mismatch;
- an auxiliary delay-locked loop having a replica structure of said primary delay-locked loop, to provide a reference time signal for calibration by aligning with an output signal of the primary delay-locked loop;
- and
- a phase detector having a charge pump, to measure a delay of one of said delay elements based on a time difference between said reference time signal and an output time signal of said delay element being measured,
- wherein said reference time signal of the auxiliary delay-locked loop is able to be realigned with an output time signal of a different one of said delay elements in the primary delay-locked loop while using the same topology.
Dependencies are inferred from the claim text.