Delay locked loop (DLL) circuit for generating clock signal for memory device
AssigneeHynix Semiconductor Inc.
InventorKwang Jin Na
Life of this patent
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Abstract
A delay locked loop (DLL) circuit is disclosed. The DLL circuit includes a first delay locked loop (DLL) configured to receive a plurality of first clock signals, delay each of the first clock signals by a predetermined period of time in response to a first control signal, and generate a plurality of first internal clock signals and a second delay locked loop (DLL) configured to receive the first internal clock signals, delay the first internal clock signals by a predetermined period of time in response to a second control signal, and generate a plurality of second internal clock signals.
Claims20
A delay locked loop (DLL) circuit comprising:
- a first delay locked loop (DLL) configured to receive a plurality of first clock signals respectively having a phase difference of a first predetermined period of time, delay each of the first clock signals by a second predetermined period of time in response to a first control signal, and generate a plurality of first internal clock signals;
- and
- a second delay locked loop (DLL) configured to receive the first internal clock signals, delay the first internal clock signals by a third predetermined period of time in response to a second control signal, and generate a plurality of second internal clock signals.
A delay locked loop (DLL) circuit comprising:
- a plurality of multiplexers for selecting and outputting a first clock signal or a second clock signal in response to a phase selection signal, the first and second clock signals having a phase difference of ½ period;
- a first delay line for delaying output signals of the multiplexers by a first predetermined period of time, and generating first internal clock signals;
- a first phase detector for comparing a phase of a feedback clock signal acquired when one of the first internal clock signals is delayed by a second predetermined period of time, with a phase of a reference clock signal, and generating a first control signal according to the comparison result;
- an initial phase controller for generating the phase selection signal in response to the first control signal, and outputting the phase selection signal to the multiplexers;
- and
- a second delay line for delaying the first internal clock signal by a third predetermined period of time, and generating a second internal clock signal.
Dependencies are inferred from the claim text.