Delay locked loop circuit
AssigneeHynix Semiconductor Inc.
InventorsHoon Choi, Jae-Jin Lee
Life of this patent
Estimating the term…
Abstract
A DLL of a memory device having a normal mode and a power down mode includes a clock buffer for buffering an external clock signal to output an internal clock signal. A power down mode controller generates a power down mode control signal to define the normal mode or the power down mode in response to a clock enable signal. A source clock generation unit receives the internal clock signal to generate a DLL source clock signal under the control of the power down mode control signal. A phase update unit performs a phase update operation based on the DLL source clock signal to output a DLL clock signal.
Claims33
A delay locked loop (DLL) of a memory device having a normal mode and a power down mode, comprising:
- a clock buffer for buffering an external clock signal to output an internal clock signal;
- a power down mode controller for generating a power down mode control signal to define the normal mode or the power down mode in response to a clock enable signal;
- a source clock generation unit for receiving the internal clock signal to generate a DLL source clock signal under the control of the power down mode control signal;
- and
- a phase update unit for performing a phase update operation based on the DLL source clock signal to output a DLL clock signal,
- wherein the source clock generation unit generates the DLL source clock signal for performing the phase update operation at least one time during the power down mode, and
- wherein the source clock generation unit includes a first clock divider for generating a first division clock signal to set a duration of the phase update operation in the normal mode by dividing the internal clock signal and a second clock divider for generating a second division clock signal to set a duration of the phase update operation in the power down mode by dividing the first division clock signal.
A delay locked loop (DLL) of a memory device having a normal mode and a power down mode, comprising:
- a clock buffer for buffering an external clock signal to output an internal clock signal;
- a power down mode controller for generating a power down mode control signal to define the normal mode or the power down mode in response to a clock enable signal;
- a source clock generation unit for receiving the internal clock signal to generate a DLL source clock signal under the control of the power down mode control signal;
- and a phase update unit for performing a phase update operation based on the DLL source clock signal to output a DLL clock signal, wherein the source clock generation unit generates the DLL source clock signal for performing the phase update operation at least one time during the power down mode, wherein the source clock generation unit includes:
- a clock divider for generating a first conversion clock signal to set a duration of the phase update operation in the normal mode by dividing the internal clock signal;
- a clock conversion unit for generating a second conversion clock signal to set a duration of the phase update operation in the power down mode by converting the first conversion clock signal;
- a selection unit for selecting one of the first and second conversion clock signals based on the power down mode control signal to thereby output the selected signal as a selection clock signal;
- and
- an operational logic unit for logically combining the selection clock signal and the internal clock signal to output the DLL source clock signal.
A delay locked loop (DLL) of a memory device having a normal mode and a power down mode, comprising:
- a clock buffer for buffering an external clock signal to output an internal clock signal;
- a power down mode controller for generating a power down mode control signal to define the normal mode or the power down mode in response to a clock enable signal;
- a source clock generation unit for receiving the internal clock signal to generate a DLL source clock signal under the control of the power down mode control signal;
- and a phase update unit for performing a phase update operation based on the DLL source clock signal to output a DLL clock signal, wherein the source clock generation unit generates the DLL source clock signal for performing the phase update operation at least one time during the power down mode, wherein the source clock generation unit includes:
- a first clock conversion unit;
- a second clock conversion unit;
- a selection unit for selecting one of output signals of the first and second clock conversion units based on the power down mode control signal to thereby output the selected signal as a selection clock signal;
- and
- an operational logic unit for logically combining the selection clock signal and the internal clock signal to output the DLL source clock signal.
A method for generating a DLL clock of a memory device having a normal mode and a power down mode, comprising:
- generating an internal clock signal by buffering an external clock;
- generating a first division clock signal by dividing the internal clock signal;
- generating a second division clock signal based on the first division clock signal;
- performing a DLL phase update operation based on the first division clock signal in the normal mode;
- and
- performing a DLL phase update operation based on the second division clock signal in the power down mode.
Dependencies are inferred from the claim text.