System and method to improve the efficiency of synchronous mirror delays and delay locked loops

A synchronous dynamic random access memory (SDRAM), comprising:

• a delay-locked loop (DLL), comprising:
• a phase detection system, comprising:
• a phase detector, the phase detector to receive a clock input signal (CIN) and a clock feedback signal (CKFB), each signal comprising timing characteristics, the phase detector comprising a pair of registers, the registers comprising a pair of inputs and a pair of outputs, each of the outputs having a logical level, to define a plurality of output signal combinations, each of the output signal combinations representative of a phase based upon the timing characteristics of the CIN and CKFB, and at least one of the phases reduces a lock period of the CIN to achieve locking with an external clock signal with respect to another phase;
• and
• an input selection multiplexor to select whether to input a clock signal (CLK) or an inverted clock signal (CLK′) into an additional component based on the logical levels of the outputs of the phase detector, the CLK and CLK′ to be provided at least indirectly from a delay line that is at least indirectly in communication with the phase detector;
• the timing characteristics the timing characteristics to include a period of CIN defined as tck and a period from a rising edge in CIN to a rising edge in CKFB defined as te, and
• a first phase is when te>tck/2;
• a second phase is when te<tck/2;
• a third phase is when te=tck;
• and
• a fourth phase is when te=tck/2.

A synchronous dynamic random access memory (SDRAM), comprising:

• a delay-locked loop (DLL), comprising:
• a phase detection system, comprising:
• a phase detector, the phase detector to receive a clock input signal (CIN) and a clock feedback signal (CKFB), each signal comprising timing characteristics, the phase detector comprising a pair of registers, the registers comprising a pair of inputs and a pair of outputs, each of the outputs comprising a logical level, the logical levels to define a plurality of output signal combinations, each of the output signal combinations representative of a phase based upon the timing characteristics of the CIN and CKFB, and at least one of the phases reduces a lock period of the CIN when input into the DLL to achieve locking with an external clock signal with respect to another phase;
• and
• an input selection multiplexor to select either an input clock signal (CLK) or an inverted clock signal (CLK′) into a clock tree driver (CTD) based on the logical levels of the outputs of the phase detector, the CLK and CLK′ to be provided at least indirectly from a delay line;
• the timing characteristics to include a period of CIN defined as tck and a period from a rising edge in CIN to a rising edge in CKFB defined as te;
• and
• a first phase is when te>tck/2;
• and
• a second phase is when te<tck/2;
• and
• a third phase is when te=tck;
• and
• a fourth phase is when te=tck/2.