Digital output driver and input buffer using thin-oxide field effect transistors

An integrated circuit comprising:

• a latch configured to provide a first digital signal having a first voltage range determined by a first supply voltage and an intermediate voltage;
• a latch driver coupled to the latch and comprising:
• a first set of at least two N-channel field effect transistors (N-FETs) stacked together and configured to pull down a first node within the latch to write a logic high to the latch, and
• a second set of at least two N-FETs stacked together and configured to pull down a second node within the latch to write a logic low to the latch;
• and
• a driver coupled to the latch and configured to receive the first digital signal and a second digital signal and to provide a digital output signal, wherein the second digital signal has a second voltage range determined by a second supply voltage and circuit ground, wherein the digital output signal has a third voltage range determined by the first supply voltage and circuit ground, and wherein the first supply voltage is higher than the second supply voltage.

An integrated circuit comprising:

• a latch configured to provide a first digital signal having a first voltage range determined by a first supply voltage and an intermediate voltage;
• an input buffer configured to receive a digital input signal having the third voltage range and to provide a buffered digital input signal having the second voltage range;
• and
• a driver coupled to the latch and configured to receive the first digital signal and a second digital signal and to provide a digital output signal, wherein the second digital signal has a second voltage range determined by a second supply voltage and circuit ground, wherein the digital output signal has a third voltage range determined by the first supply voltage and circuit ground, and wherein the first supply voltage is higher than the second supply voltage.

An integrated circuit comprising:

• an output driver configured
• to receive an internal input signal having a first voltage range determined by a first supply voltage and an intermediate voltage,
• to generate a first digital signal having the first voltage range,
• to generate a second digital signal having a second voltage range determined by a second supply voltage and circuit ground, and
• to provide a digital output signal having a third voltage range determined by the first supply voltage and circuit ground, wherein the first supply voltage is higher than the second supply voltage;
• and
• an input buffer configured to receive an external input signal having the third voltage range and to provide a buffered input signal having the second voltage range.