US 7,605,617 B2 · Method for switching a system clock and clock synchronization unit

Abstract

A clock synchronization unit is provided for an electronic system, particularly for a microprocessor, that includes a first input for a first clock signal, a second input for a second clock signal, a third input for a select control signal, and an output for a system clock signal. A first control module controlled by the first clock signal, a second control module controlled by the second clock signal and connected to the first control module in terms of signaling technique is also provided. The first control module upon application of a predefined signal level of the select control signal at the third input synchronously with the first dock signal, is designed to set the system clock signal from the first clock signal to a predefined logic signal level as the system clock hold signal, and the second control module is designed, synchronously with the second clock signal, to reset the system clock hold signal and to cause an output of the second clock signal as the system clock signal.

Claims15

Dependent claims

A method for switching a system clock from a first clock signal to a second clock signal, the switching process is triggered by a select control signal and the switching occurs synchronously to the first and/or second clock signal, the method comprising:

transferring the clock control from a first predefined edge of the first clock signal to a corresponding first edge of the second clock signal;
holding, in accordance with the first clock signal, a system clock signal at a first predefined logic signal level which is the same level as a system clock hold signal, wherein a corresponding first edge of the second clock signal is awaited;
and
resetting, in accordance with a received first edge of the second clock signal, the system clock hold signal to a second logic state and reactivating, via a second edge of the second clock signal, the system clock signal whereby the second clock functions as the system clock.

1 more element

A clock synchronization unit for an electronic system, particularly for a microprocessor, the clock synchronization unit comprising:

a first input for a first clock signal;
a second input for a second clock signal;
a third input for a select control signal;
an output for a system clock signal;
a first control module controlled by the first clock signal;
and
a second control module controlled by the second clock signal and being operatively connected to the first control module,
wherein the first control module, upon application of a predefined signal level of the select control signal at a third input synchronously with the first clock signal, is designed to set the system clock signal from the first clock signal to a predefined logic signal level as a system clock hold signal, and
wherein the second control module is designed, synchronously with the second clock signal, to reset the system clock hold signal and to cause an output of the second clock signal as the system clock signal.

6 more elements

Dependencies are inferred from the claim text.

Method for switching a system clock and clock synchronization unit

Life of this patent

Method for switching a system clock and clock synchronization unit

Life of this patent

Abstract

Claims15