US 7,605,615 B2Granted

Voltage comparator circuit

AssigneeNEC Electronics Corporation

InventorAkira Yukawa

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Abstract

There is provided a voltage comparator circuit with even lower power consumption. It comprises an FET Q1, to the gate of which a signal input terminal IN1 is connected, an FET Q2, to the gate of which a signal input terminal IN2 is connected, a bistable circuit, an AND circuit G, and an FET Q11. A pulse signal φ, which becomes a strobe signal for the comparison, is supplied to the bistable circuit, and when the pulse signal φ is at a low level, the logic values of output terminals OUT1 and OUT2 go to a high level, and the output of the AND circuit G becomes high, turning the FET Q11 on. When the pulse signal φ changes to a high level from a low level, input voltages are compared, one of the output terminals OUT1 or OUT2 changes to a low level, corresponding to the value relationship between the drain currents of the FETs Q1 and Q2, and the output of the AND circuit G goes to a low level, turning the FET Q11 off. The power consumption is reduced because the source currents of the FETs Q1 and Q2 flow only during a short period of time when the operation of comparison is being performed.

A voltage comparator circuit, comprising:

an amplifier including a constant current input, a first input field effect transistor configured to receive a first input signal and a second input field effect transistor configured to receive a second input signal;
a pulse signal generator configured to output a pulse signal;
a double bistable circuit being configured to receive the pulse signal so that when the pulse signal is at a low level, a first output terminal configured to output a first output signal and a second output terminal configured to output a second output signal both output a high level and when the pulse signal changes to a high level, either one of the first output terminal and the second output terminal changes to a low level corresponding to a value relationship between a drain current of the first input field effect transistor and a drain current of the second input field effect transistor;
a logic circuit configured to receive the first output signal and the second output signal from the double bistable circuit, the logic circuit being configured to supply the amplifier with power when the output is high and to not supply the amplifier with power when the output is low;
a first switch field effect transistor having a drain electrode in common with a source electrode of the first input field effect transistor and a drain electrode in common with a source electrode of the second input field effect transistor, and the source electrode of the first switch field effect transistor being connected to a low potential power supply;
a second switch field effect transistor having a drain electrode and a gate electrode being connected in common to a constant current source and a source electrode thereof being connected to the low potential power supply;
and
a third switch field effect transistor having a drain electrode thereof in common with a drain electrode of a fourth switch field effect transistor and the gate electrode of the second field effect transistor, and the source electrode of the third switch field effect transistor being connected to the drain electrode of the second switch field effect transistor, the fourth switch field effect transistor having a drain electrode in common with the drain electrode of the third switch field effect transistor and a drain electrode in common with the sate electrode of the second switch field effect transistor, and a source electrode of the fourth switch field effect transistor being connected to the low potential power supply.

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Abstract

Claims5