Techniques for reducing power requirements of an integrated circuit

A method for clock gating a clock domain of an integrated circuit, comprising:

• storing first, second, and third values in a control register, wherein the first value corresponds to a first number of clock cycles to wait before initiating clock gating, the second value corresponds to a second number of clock cycles in which clock gating is performed, and the third value corresponds to a third number of clock cycles in which clock gating is not performed;
• selectively loading one of the first, second, and third values from the control register into a counting circuit;
• counting, using the counting circuit, from the loaded one of the first, second, and third values to a transition value;
• receiving, at a control state machine, a compare signal from the counting circuit that indicates the counting circuit has reached the transition value;
• and
• providing, based on a current state of the control state machine, a load signal to the counting circuit to cause the counting circuit to load an associated one of the first, second, and third values from the control register.

A method for clock gating a clock domain of an integrated circuit, comprising:

• storing first, second, and third values in a control register, wherein the first value corresponds to a first number of clock cycles to wait before initiating clock gating, the second value corresponds to a second number of clock cycles in which clock gating is performed, and the third value corresponds to a third number of clock cycles in which clock gating is not performed;
• selectively loading one of the first, second, and third values from the control register into a counting circuit;
• counting, using the counting circuit, from the loaded one of the first, second, and third values to a transition value;
• receiving, at a control state machine, a compare signal from the counting circuit that indicates the counting circuit has reached the transition value;
• and
• providing, based on a current state of the control state machine, a load signal to the counting circuit to cause the counting circuit to load an associated one of the first, second, and third values from the control register while an associated enable signal is asserted.