Programmable level shifter

An integrated circuit having a programmable level shifter adapted to selectively operate in either a high-speed mode or a low-power mode to convert an input signal in a first power supply domain into an output signal in a second power supply domain different from the first power supply domain, wherein:

• switching speed of the level shifter is higher in the high-speed mode than in the low-power mode;
• power consumption of the level shifter is lower in the low-power mode than in the high-speed mode;
• and
• the programmable level shifter comprises:
• first and second p-type devices that are configured as a current-mirror amplifier in the high-speed mode and as a cross-coupled latch in the low-power mode;
• third and fourth p-type devices that are controlled by a mode-control signal to configure the first and second p-type devices (1) as the current-mirror amplifier for the high-speed mode and (2) as the cross-coupled latch for the low-power mode;
• first, second, third, and fourth n-type devices, wherein the first and third n-type devices are connected in parallel;
• the second and fourth n-type devices are connected in parallel;
• in the high-speed mode, the third and fourth n-type devices are disabled;
• and in the low-power mode, the third and fourth n-type devices are enabled, such that (1) the first and third n-type devices form a first relatively large effective n-type device and (2) the second and fourth n-type devices form a second relatively large effective n-type device;
• and
• first and second muxes that are controlled by the mode-control signal to (1) disable the third and fourth n-type devices for the high-speed mode and (2) enable the third and fourth n-type devices for the low-power mode.

An integrated circuit comprising:

• first means for converting, in a high-speed mode, an input signal in a first power supply domain into an output signal in a second power supply domain different from the first power supply domain;
• and
• second means for converting, in a low-power mode, the input signal in the first power supply domain into the output signal in the second power supply domain, wherein:
• switching speed of the first means is higher than switching speed of the second means;
• power consumption of the first means is lower than power consumption of the second means;
• the first and second means share first and second devices that are configured as a current-mirror amplifier in the first means and as a cross-coupled latch in the second means,
• wherein:
• the second means further comprises first, second, third, and fourth n-type devices;
• the first and third n-type devices are connected in parallel in the second means to form a first relatively large effective n-type device;
• the second and fourth n-type devices are connected in parallel in the second means to form a second relatively large effective n-type device;
• and
• the first and second means share the first and third n-type devices, but not the second and fourth n-type devices.

An integrated circuit having a programmable level shifter adapted to selectively operate in either a high-speed mode or a low-power mode to convert an input signal in a first power supply domain into an output signal in a second power supply domain different from the first power supply domain, wherein:

• switching speed of the level shifter is higher in the high-speed mode than in the low-power mode;
• power consumption of the level shifter is lower in the low-power mode than in the high-speed mode;
• the programmable level shifter comprises first, second, third, and fourth devices, wherein:
• the first and third devices are connected in parallel;
• the second and fourth devices are connected in parallel;
• in the high-speed mode, the third and fourth devices are disabled;
• and
• in the low-power mode, the third and fourth devices are enabled, such that (1) the first and third devices form a first relatively large effective device and (2) the second and fourth devices form a second relatively large effective device;
• and
• the programmable level shifter further comprises first and second muxes that are controlled by a mode-control signal to (1) disable the third and fourth devices for the high-speed mode and (2) enable the third and fourth devices for the low-power mode.