Circuit for converting a voltage range of a logic signal

A circuit to convert a first logic signal having a first range to a pair of complementary second logic signals having a second range, comprising:

• a first transistor to selectively couple a first output node to a first reference voltage when the first output node is to be in a first state;
• a second transistor to selectively discharge the first output node toward a second reference voltage when the first output node is to transition from the first state to a second state, the second state being a logical complement of the first state;
• a first source-follower circuit having a source follower output coupled to the first output node and having a current source;
• and
• a third transistor to selectively couple the current source of the first source-follower circuit to the second reference voltage when the first output node is to be in the second state;
• a fourth transistor to selectively couple a second output node to the first reference voltage when the second output node is to be in the first state;
• a fifth transistor to selectively discharge the second output node toward the second reference voltage when the second output node is to transition from the first state to the second state;
• a second source-follower circuit having a source follower output coupled to the second output node and having a current source;
• and
• a sixth transistor to selectively couple the current source of the second source-follower circuit to the second reference voltage when the second output node is to be in the second state.

A circuit to convert a first logic signal having a first range to at least one second logic signal having a second range, comprising:

• a first p-channel metal oxide semiconductor (PMOS) transistor having a gate coupled to a first control signal, a source coupled to a first reference voltage, and a drain coupled to a first output node;
• a second PMOS transistor having a gate coupled to a second control signal, the second control signal a logical complement of the first control signal, the second PMOS transistor having a source coupled to the first output node and a drain coupled to a second reference voltage;
• a first n-channel metal oxide semiconductor (NMOS) transistor having a gate coupled to a first bias voltage, a source coupled to the first output node, and a drain coupled to the first reference voltage;
• a second NMOS transistor having a gate coupled to a second bias voltage and a drain coupled to the first output node;
• a third NMOS transistor having a gate coupled to the first control signal, a source coupled to the second reference voltage, and a drain coupled to a source of the second NMOS transistor;
• wherein a minimum voltage of the first output node when the first control signal is HIGH is within the range 100 millivolts and 350 millivolts, inclusive.

A cell of a current steering digital-to-analog converter, comprising:

• a current source;
• a first p-channel metal oxide semiconductor (PMOS) transistor having a source coupled to the current source and a drain coupled to a current summing line;
• a second PMOS transistor having a source coupled to the current source and a drain coupled to a reference node;
• a driver circuit having an input, a first output coupled to a gate of the first PMOS transistor, and a second output coupled to a gate of the second PMOS transistor;
• wherein the driver circuit comprises:
• a third PMOS transistor having a gate coupled to a first control signal, a source coupled to a first reference voltage, and a drain coupled to the first output of the driver circuit;
• a fourth PMOS transistor having a gate coupled to a second control signal, the second control signal being a logical complement of the first control signal, the fourth PMOS transistor having a source coupled to the first output of the driver circuit and a drain coupled to a second reference voltage;
• a first n-channel metal oxide semiconductor (NMOS) transistor having a gate coupled to a first bias voltage, a source coupled to the first output of the driver circuit, and a drain coupled to the first reference voltage;
• a second NMOS transistor having a gate coupled to a second bias voltage and a drain coupled to the first output of the driver circuit;
• a third NMOS transistor having a gate coupled to the first control signal, a source coupled to the second reference voltage, and a drain coupled to a source of the second NMOS transistor;
• a fifth PMOS transistor having a gate coupled to the second control signal, a source coupled to the first reference voltage, and a drain coupled to the second output of the driver circuit;
• a sixth PMOS transistor having a gate coupled to the first control signal, a source coupled to the second output of the driver circuit, and a drain coupled to the second reference voltage;
• a fourth NMOS transistor having a gate coupled to the first bias voltage, a source coupled to the second output of the driver circuit, and a drain coupled to the first reference voltage;
• a fifth NMOS transistor having a gate coupled to the second bias voltage and a drain coupled to the second output of the driver circuit;
• a sixth NMOS transistor having a gate coupled to the second control signal, a source coupled to the second reference voltage, and a drain coupled to a source of the fifth NMOS transistor;
• wherein a minimum voltage of the first output of the driver circuit when the first control signal is HIGH is within the range 100 millivolts to 350 millivolts, inclusive;
• wherein a minimum voltage of the second output of the driver circuit when the second control signal is HIGH is within the range 100 millivolts to 350 millivolts, inclusive.