User-accessible freeze-logic for dynamic power reduction and associated methods
AssigneeAltera Corporation
InventorsMichael D. Hutton, Andy L. Lee
Life of this patent
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Abstract
A programmable logic device (PLD) includes a configuration circuit, and first and second freeze-logic circuits. The configuration circuit provides configuration data for configuring programmable resources of the PLD during a configuration mode of the PLD. One of the two freeze-logic circuits provides a freeze logic signal during the configuration mode of the PLD. The other freeze-logic circuit provides a freeze logic signal during a user mode of the PLD.
Claims14
A programmable logic device (PLD), comprising:
- a configuration circuit that provides configuration data for configuring programmable resources of the programmable logic device (PLD) during a configuration mode of the programmable logic device (PLD);
- a first freeze-logic circuit that provides a first freeze logic signal during the configuration mode of the programmable logic device (PLD);
- and
- a second freeze-logic circuit that provides a second freeze logic signal during a user mode of the programmable logic device (PLD).
A programmable logic device (PLD), comprising:
- a logic array block, comprising:
- a first logic element that provides a first signal that a user of the programmable logic device (PLD) may freeze during a user mode of the programmable logic device (PLD),
- wherein the first signal is frozen by using a combinational freeze signal.
A method of operating a programmable logic device (PLD), the method comprising:
- using a first freeze-logic signal during a configuration mode of the programmable logic device (PLD);
- and
- using a second freeze-logic signal during a user mode of the programmable logic device (PLD).
Dependencies are inferred from the claim text.