Stacked die semiconductor package
AssigneeSTMicroelectronics S.r.l.
InventorAlex Gritti
Life of this patent
Estimating the term…
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AssigneeSTMicroelectronics S.r.l.
InventorAlex Gritti
Estimating the term…
A stacked die semiconductor package includes: a substrate, having a first surface and an opposite surface thereto; a plurality of dice, structured for being stacked one on top of the other on the first surface of the substrate, including at least a first die which is mounted closest to the first surface, a second die mounted thereupon and having a larger footprint area than the first die, and a top die having a smaller footprint area than the underlying die thereof, and each having a plurality of contact pads and a plurality of wires for electrically connecting the dice to the first surface of the substrate; at least one interposer between the plurality of dice; advantageously, said top die is electrically directly connected to one of the underlying dice. A method for the assembly of a stacked die semiconductor package is provided.
A stacked die semiconductor package, comprising:
A stacked die semiconductor package, comprising:
A stacked die semiconductor package, comprising:
A stacked die semiconductor package, comprising:
Dependencies are inferred from the claim text.