Bi-directional MOSFET power switch with single metal layer

A monolithic semiconductor device, comprising:

• a substrate;
• a well region formed over the substrate;
• a first channel region formed in the well region;
• a first source region formed adjacent to the first channel region;
• a first metal layer in electrical contact with the first source region;
• a first gate region formed over the first channel region;
• a second channel region formed in the well region;
• a second source region formed adjacent to the second channel region;
• a second metal layer in electrical contact with the second source region, wherein the first and second metal layers are formed in a first plane;
• a second gate region formed over the second channel region;
• a common drain region disposed between the first and second gate regions;
• a first electrostatic protection diode coupled between the first gate region and first source region;
• and
• a second electrostatic protection diode coupled between second gate region and second source region.

An integrated circuit, comprising:

• a semiconductor device including,
• (a) a substrate,
• (b) a well region formed over the substrate,
• (c) a first transistor having a first channel region formed in the well region, a first source region formed adjacent to the first channel region, a first metal layer in electrical contact with the first source region, and a first gate region formed over the first channel region,
• (d) a second transistor having a second channel region formed in the well region, a second source region formed adjacent to the second channel region, a second metal layer in electrical contact with the second source region, wherein the first and second metal layers are formed and interdigitated in the same plane, and a second gate region formed over the second channel region, and
• (e) a common drain region disposed between the first and second gate regions of the first and second transistors;
• and
• a control circuit having a first output coupled to the first gate region and a second output coupled to the second gate region.