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US 7,605,434 B2Granted
Semiconductor memory device to which test data is written
AssigneeKabushiki Kaisha Toshiba
InventorTomohito Kawano
Life of this patent
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Abstract
A semiconductor memory device of this invention includes a first bank, a second bank, and a bank decoder that selects a bank to be activated from the first and second banks. When testing operations of first memory cells and second memory cells, the bank decoder simultaneously selects the first and second banks, and first and second write load circuits simultaneously write data in memory cells in first and second blocks, respectively.
Claims16
A semiconductor memory device comprising:
- a first bank including
- a first block in which a plurality of first memory cells are arranged in a matrix;
- a plurality of first bit lines connected to said plurality of first memory cells;
- a first data line connected to even-numbered bit lines of said plurality of first bit lines via a column selection transistor, and a second data line connected to odd-numbered bit lines of said plurality of first bit lines via a column selection transistor;
- and
- a first write load circuit which applies a first write voltage corresponding to write data to the first data line and the second data line at the time of data write,
- a second bank including
- a second block in which a plurality of second memory cells are arranged in a matrix;
- a plurality of second bit lines connected to said plurality of second memory cells;
- a third data line connected to even-numbered bit lines of said plurality of second bit lines via a column selection transistor, and a fourth data line connected to odd-numbered bit lines of said plurality of second bit lines via a column selection transistor;
- and
- a second write load circuit which applies a second write voltage corresponding to write data to the third data line and the fourth data line at the time of data write, and
- a bank decoder which selects a bank to be activated from the first bank and the second bank,
- wherein when testing operations of said plurality of first memory cells and said plurality of second memory cells, the bank decoder simultaneously selects the first bank and the second bank, and the first write load circuit and the second write load circuit simultaneously write data in memory cells in the first block and memory cells in the second block.
11 more elements
A semiconductor memory device comprising:
- a first block in which a plurality of first memory cells are arranged in a matrix, the first block being formed in a bank;
- a plurality of first bit lines connected to said plurality of first memory cells in the first block;
- a second block in which a plurality of second memory cells are arranged in a matrix, the second block being formed in the bank;
- a plurality of second bit lines connected to said plurality of second memory cells in the second block;
- a first data line connected to even-numbered bit lines of said plurality of first bit lines and said plurality of second bit lines via a column selection transistor;
- a second data line connected to odd-numbered bit lines of said plurality of first bit lines and said plurality of second bit lines via a column selection transistor;
- a write load circuit which applies a write voltage corresponding to write data to the first data line and the second data line at the time of data write;
- and
- a block decoder which selects a block to be activated from the first block and the second block,
- wherein when testing operations of said plurality of memory cells, the block decoder simultaneously selects the first block and the second block, and the write load circuit simultaneously writes data in memory cells in the first block and memory cells in the second block.
7 more elements
Dependencies are inferred from the claim text.